Fedata_Reg-Fault Event Data Register; Feaddr_Reg-Fault Event Address Register; Feuaddr_Reg-Fault Event Upper Address Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.21.10 FEDATA_REG—Fault Event Data Register
This register specifies the interrupt message data.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:16
15:0
2.21.11 FEADDR_REG—Fault Event Address Register
Register specifying the interrupt message address.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:2
1:0
2.21.12 FEUADDR_REG—Fault Event Upper Address Register
This register specifies the interrupt message upper address.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:0
276
0/0/0/VC0PREMAP
3C–3Fh
00000000h
RW
32 bits
Reset RST/
Attr
Value PWR
RW 0000h Uncore
RW 0000h Uncore
0/0/0/VC0PREMAP
40–43h
00000000h
RW
32 bits
0h
Reset RST/
Attr
Value PWR
RW 00000000h Uncore
RO 0h
0/0/0/VC0PREMAP
44–47h
00000000h
RW
32 bits
Reset RST/
Attr
Value PWR
RW 00000000h Uncore
Processor Configuration Registers
Description
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt data
may treat this field as RsvdZ.
Interrupt Message Data (IMD)
Data value in the interrupt request.
Description
Message Address (MA)
When fault events are enabled, the contents of this register specify
the DWORD-aligned address (bits 31:2) for the interrupt request.
Reserved
Description
Message upper address (MUA)
Hardware implementations supporting Extended Interrupt Mode
are required to implement this register.
Hardware implementations not supporting Extended Interrupt
Mode may treat this field as RsvdZ.
Datasheet, Volume 2