Pcists2-Pci Status Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.8.4 PCISTS2—PCI Status Register
PCISTS is a 16-bit statu s register that reports the occurrence of a PCI compliant master
abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that
has been set by the IGD.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Datasheet, Volume 2
0/2/0/PCI
6–7h
0090h
RO, RO-V
16 bits
0h
Reset RST/
Attr
Value PWR
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 0b Uncore
RO 00b Uncore
RO 0b Uncore
RO 1b Uncore
RO 0b Uncore
RO 0b Uncore
RO 1b Uncore
RO-V 0b Uncore
RO 0h
Description
Detected Parity Error (DPE)
Since the IGD does not detect parity, this bit is always hardwired to
0.
Signaled System Error (SSE)
The IGD never asserts SERR#; therefore, this bit is hardwired to 0.
Received Master Abort Status (RMAS)
The IGD never gets a Master Abort; therefore, this bit is hardwired
to 0.
Received Target Abort Status (RTAS)
The IGD never gets a Target Abort; therefore, this bit is hardwired
to 0.
Signaled Target Abort Status (STAS)
Hardwired to 0. The IGD does not use target abort semantics.
DEVSEL Timing (DEVT)
Not applicable. These bits are hardwired to "00".
Master Data Parity Error Detected (DPD)
Since Parity Error Response is hardwired to disabled (and the IGD
does not do any parity detection), this bit is hardwired to 0.
Fast Back-to-Back (FB2B)
Hardwired to 1. The IGD accepts fast back-to-back when the
transactions are not to the same agent.
User Defined Format (UDF)
Hardwired to 0.
66 MHz PCI Capable (C66)
Not applicable. Hardwired to 0.
Capability List (CLIST)
This bit is set to 1 to indicate that the register at 34h provides an
offset into the function's PCI Configuration Space containing a
pointer to the location of the first item in the list.
Interrupt Status (INTSTS)
This bit reflects the state of the interrupt in the device. Only when
the Interrupt Disable bit in the Command register is a 0 and this
Interrupt Status bit is a 1, will the devices INTx# signal be
asserted.
Reserved
131