Jtag States - Motorola M68060 User Manual

IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
toggling (such as during in-circuit testing) by placing all system signal pins to a high
impedance state.
The IEEE standard 1149.1 test logic cannot be considered com-
pletely benign to those planning not to use this capability. Cer-
tain precautions must be observed to ensure that this logic does
not interfere with system operation and allows full use of the
LPSTOP function. Refer to 9.1.5 Disabling the IEEE 1149.1
Standard Operation
9.1.1 Overview
Figure 9-1 illustrates the block diagram of the MC68060 implementation of the 1149.1 stan-
dard.The test logic includes several test data registers, an instruction register, instruction
register control decode, and a 16-state dedicated TAP controller. The sixteen controller
states are defined in detail in the in the IEEE 1149.1 standard, but eight are listed in Table
9-1 and included for illustration purposes:
State Name
Test-Logic-Reset
Run-Test-Idle
Capture-IR
Shift-IR
Update-IR
Capture-DR
Shift-DR
Update-DR
The TAP consists of five dedicated signal pins which are controlled by a sixth dedicated
compliance enable pin.
1. JTAG—An active low JTAG enable pin that maps the TAP signals to either the 1149.1
logic or the emulation mode logic and meets the requirements set forth for a compli-
ance enable pin. The TAP pins are described in the case of JTAG asserted.
2. TCK—A test clock input that synchronizes test logic operations.
3. TMS—A test mode select input with an internal pullup resistor that is sampled on the
rising edge of TCK to sequence the TAP controller.
4. TDI—A serial test data input with an internal pullup resistor that is sampled on the ris-
ing edge of TCK.
5. TDO—A three-state test data output that is actively driven only in the shift-IR and shift-
DR controller states and only updates on the falling edge of TCK.
6. TRST—An active low asynchronous reset with an internal pullup resistor that forces
the TAP controller into the test-logic-reset state.
9-2
NOTE
Table 9-1. JTAG States
State Summary
Places test logic in default defined reset state
Allows test control logic to remain idle while test operations
occur
Loads default IDCODE instruction into the instruction register
Allows serial data to move from TDI to TDO through the instruc-
tion register
Applies and activates instruction contained in the instruction
shift register
Loads parallel sampled data into the selected test data register
Allows serial data to move from TDI to TDO through the selected
test data register
Applies test data contained in the selected test data register
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