Idle Mode; Setting And Operation Status; Releasing Idle Mode - NEC V850ES/KE1+ User Manual

32-bit single-chip microcontrollers
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19.4 IDLE Mode

19.4.1 Setting and operation status

The IDLE mode is set by clearing the PSMR.PSM bit to 0 and setting the PSC.STP bit to 1 in the normal operation
mode.
In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral
functions stops.
As a result, program execution stops and the contents of the internal RAM before the IDLE mode was set are
retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions
that can operate with the subclock, internal oscillation clock, or an external clock continue operating.
Table 19-5 shows the operation status in the IDLE mode.
The IDLE mode can reduce the power consumption more than the HALT mode because it stops the operation of
the on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be
restored without waiting for the oscillation stabilization time after the IDLE mode has been released, in the same
manner as when the HALT mode is released.
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
set the IDLE mode.

19.4.2 Releasing IDLE mode

The IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal
from the peripheral functions operable in the IDLE mode, or reset (except WDTRES1 signal).
After the IDLE mode has been released, the normal operation mode is restored.
(1) Releasing IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request. If the IDLE mode is set in an interrupt
servicing routine, however, an interrupt request that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, only the IDLE mode is released, and that interrupt request signal is not acknowledged. The
interrupt request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being
serviced is issued (including a non-maskable interrupt request signal), the IDLE mode is released and that
interrupt request signal is acknowledged.
Table 19-4. Operation After Releasing IDLE Mode by Interrupt Request Signal
Release Source
Non-maskable interrupt request signal
Maskable interrupt request signal
Caution The interrupt request signal that is disabled by setting the PSC.NMI2M, PSC.NMI0M, and
PSC.INTM bits to 1 becomes invalid and IDLE mode is not released.
580
CHAPTER 19 STANDBY FUNCTION
Interrupt Enabled (EI) Status
Execution branches to the handler address
Execution branches to the handler
address or the next instruction is
executed
User's Manual U16896EJ2V0UD
Interrupt Disabled (DI) Status
The next instruction is executed

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