Idle Mode - NEC V850/SB1 User Manual

6.4.3 IDLE mode

(1) Settings and operating states
This mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the
clock oscillator is still operating. Supply to the subclock continues. When this mode is released, there is no need
for the oscillator to wait for the oscillation stabilization time, so normal operation can be resumed quickly.
In IDLE mode, program execution is stopped and the contents of all registers and internal RAM are retained as
they were just before IDLE mode was set. In addition, on-chip peripheral functions are stopped (except for
peripheral functions that are operating with the subclock).
acknowledged.
When the IDLE bit of the power saving control register (PSC) is set to 1, the system switches to IDLE mode.
The operating statuses in IDLE mode are listed in Table 6-2.
(2) Release of IDLE mode
IDLE mode can be released by a non-maskable interrupt, an unmasked interrupt request, or RESET input.
IDLE Mode Settings
Item
CPU
ROM correction
Clock generator
16-bit timer (TM0)
16-bit timer (TM1)
8-bit timer (TM2)
8-bit timer (TM3)
8-bit timer (TM4)
8-bit timer (TM5)
8-bit timer (TM6)
8-bit timer (TM7)
Watch timer
Watchdog timer
Serial CSI0 to CSI3
interface
2 Note 2 Note
I C0 , I C1
UART0, UART1 Operates when an external clock is selected as the baud-rate clock (transmit only)
CSI4
IEBus (V850/SB2 only)
A/D converter
DMA0 to DMA5
Real-time output
Port function
Note Available only in the Y versions (products with on-chip I
192
CHAPTER 6 CLOCK GENERATION FUNCTION
Table 6-2. Operating Statuses in IDLE Mode (1/2)
When Subclock Exists
Stopped
Stopped
Both main clock and subclock oscillator
Clock supply to CPU and on-chip peripheral functions is stopped
Operates when INTWTNI is selected as count
clock (f is selected for watch timer)
XT
Stopped
Stopped
Stopped
Operates when f is selected for count clock
XT
Operates when f is selected for count clock
XT
Operates when TO0 is selected as count clock (however, only when TM0 is operating)
Operates when TO0 is selected as count clock (however, only when TM0 is operating)
Operating
Stopped
Operates when an external clock is selected as the serial clock
Stopped
Operates when an external clock is selected as the serial clock
Stopped
Stopped
Stopped
Operates when INTTM4 or INTTM5 is
selected (when TM4 or TM5 is operating)
Held
User's Manual U13850EJ6V0UD
External bus hold requests (HLDRQ) are not
When Subclock Does Not Exist
Stopped
Stopped
Stopped
Stopped
2
C).