Selecting Input Clock; Direct Mode; Pll Mode - NEC V854 UPD703006 User Manual

6.3 Selecting Input Clock

The clock generator consists of an oscillator and a PLL synthesizer. It generates, for example, a 32.768 (Max. 33)-
MHz internal system clock ( φ ) when a 6.5536-MHz crystal resonator or ceramic resonator is connected across the
X1 and X2 pins at 5-x multiplication.
An external clock can be directly connected to the oscillator circuit. In this case, input the clock signal to the X1
pin, and leave the X2 pin open.
The clock generator is provided with two basic operation modes: PLL mode and direct mode. The operation modes
are selected by the CKSEL pin. The CKSEL pin is latched at reset.
Caution Use CKSEL pin with a fixed input level. Changing the level during operations of this pin may cause
erroneous operation.

6.3.1 Direct mode

In the direct mode, external clock with frequency twice higher than that of the internal system clock is input. Because
the oscillator circuit and PLL synthesizer do not run, power consumption is significantly reduced. This mode is mainly
used for application systems that operate the V854 in a relatively low frequency. Considering EMI measures, the
PLL mode is recommended when the external clock frequency (f
or more.

6.3.2 PLL mode

In the PLL mode, an external clock is input by connecting an external oscillator, which is multiplied by the PLL
synthesizer to generate the internal system clock ( φ ).
The PLL multiplication number that can be selected is either one or five. The PLL multiplication number can be
selected by the PLLSEL pin (refer to 2.3.16 PLLSEL).
Cautions 1. Fix the PLLSEL pin so that the input level does not change (changing the input level of this
pin during operation may cause erroneous operation). When this pin is set in the direct mode
(CKSEL = 1), the PLLSEL pin has no function. Treat it as an unused pin.
2. When using an external by a resonator, use this mode with f
At reset, with reference to the input clock frequency (f
the base clock (1 x f ) or five times the base clock (5 x f
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is selected.
In the PLL mode, when the clock supply from the external oscillator or external clock source is stopped, the internal
system clock ( φ ) based on the freerunning frequency of the voltage-controlled oscillator circuit (VCO) in the clock
generator continues operating. In this case, φ is approximately 1 MHz (target). Do not use this mode expecting to
obtain the freerunning frequency.
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CHAPTER 6 CLOCK GENERATOR FUNCTION
CKSEL Operation Mode
0 PLL mode
1 Direct mode
PLLSEL Multiplication
0 1-x multiplication
1 5-x multiplication
), an internal system clock ( φ ) that is either equivalent to
XX
) is generated depending on whether 1-x or 5-x multiplication
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User's Manual U11969EJ3V0UM00
) is 32 MHz (internal system clock ( φ ) = 16 MHz)
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= 16 MHz max.
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