Control Registers; Clock Control Register (Ckc); Figure 9-2: Clock Control Register (Ckc) (1/2) - NEC V850E/CA2 JUPITER Preliminary User's Manual

9.3 Control Registers

9.3.1 Clock Control Register (CKC)

This is an 8-bit register that controls the clock management. Data can be written to it only in a sequence
of specific instructions so that its contents are not easily rewritten in case of program hang-up. See also
PHCMD register.
This register can be read or written in 8-bit units.
7 6
CKC PLLEN SCEN
Bit name
PLLEN enable bit
This bit enables or disables PLL operation.
0: PLL disabled
1: PLL enabled
Caution: The PLL is enabled when this bit is set (1). Before applying the PLL clock as the
PLLEN
SSCG enable bit
This bit enables or disables Spread-Spectrum-Clock-Generation
0: SSCG disabled
1: SSCG enabled
Caution: The SSCG is enabled when this bit is set (1). Before applying the SSCG clock
SCEN
SSCG frequency dithering enable bit
0: SSCG uses fixed multiplication factor of SCFC1
DEN
1: SSCG uses multiplication factor of SCFC0 and SCFC1 alternately
Caution: The DEN bit can be toggled only in case that the SCEN bit is 0 (SSCG disabled).
Peripheral clock source select bit
PERIC 0: Main oscillator (x1) is clock source for peripherals
1: PLL (x4) is clock source for peripherals
Chapter 9 Clock Generator

Figure 9-2: Clock Control Register (CKC) (1/2)

5 4 3
DEN 0 PERIC
clock supply for the CPU or the peripherals, it must have been secured by soft-
ware that the PLL stabilization time (1ms) has been elapsed. During this stabili-
zation time, the software must remain in a loop and the CPU and the
peripherals are supplied by the main-oscillator clock.
Switching to an unstable clock source is not protected by hardware.
as the clock supply for the CPU, it must have been secured that the SSCG sta-
bilization time has been elapsed. The SCSTAT bit in the CGSTAT register shows
the status of the SSCG. The value of the read-only bit SCSTAT must be read as
set (1) before enabling the SSCG clock to the CPU.
Switching to an unstable clock source is not protected by hardware.
Preliminary User's Manual U15839EE1V0UM00
2 1 0
0 WTSEL1 WTSEL0
Function
Initial
Address
value
FFFFF822H 00H
241