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8.2 Non-Maskable Interrupts
A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the
interrupt disabled (DI) status.
Non-maskable interrupts of V850E/CA2 are available for the following two requests:
• NMI pin input
• Non-maskable watchdog timer interrupt request
When the valid edge specified by the ESN0 bit of the Interrupt mode register 3 (INTM3) is detected on
the NMI pin, the interrupt occurs.
The watchdog timer interrupt request is only effective as non-maskable interrupt if the WDTM3 bit of the
watchdog timer mode register (WDTM) is set 0.
If multiple non-maskable interrupts are generated at the same time, the highest priority servicing is exe-
cuted according to the following priority order (the lower priority interrupt is ignored):
NMIWDT > NMI0
Note that if a NMI from port pin or NMIWDT request is generated while NMI from port pin is being serv-
iced, the service is executed as follows.
(1)
If a NMI0 is generated while NMI0 is being serviced
The new NMI0 request is held pending regardless of the value of the PSW.NP bit. The pending
NMIVC request is acknowledged after servicing of the current NMI0 request has finished (after
execution of the RETI instruction).
(2)
If a NMIWDT request is generated while NMI0 is being serviced
If the PSW.NP bit remains set (1) while NMI0 is being serviced, the new NMIWDT request is held
pending. The pending NMIWDT request is acknowledge after servicing of the current NMI0
request has finished (after execution of the RETI instruction).
If the PSW.NP bit is cleared (0) while NMI0 is being serviced, the newly generated NMIWDT
request is executed (NMI0 servicing is halted).
Remark:
PSW.NP: The NP bit of the PSW register.
Cautions: 1. Although the values of the PC and PSW are saved to an NMI status save register
(FEPC, FEPSW) when a non-maskable interrupt request is generated, only the
NMI0 can be restored by the RETI instruction at this time. Because NMIWDT can-
not be restored by the RETI instruction, the system must be reset after servicing
this interrupt.
2. If PSW.NP is cleared to 0 by the LDSR instruction during non-maskable interrupt
servicing, a NMI0 interrupt afterwards cannot be acknowledged correctly.
Chapter 8 Interrupt/Exception Processing Function
Preliminary User's Manual U15839EE1V0UM00
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