Non-Maskable Interrupts - NEC Renesas V850/SC1 User Manual

7.2 Non-Maskable Interrupts

Non-maskable interrupts are acknowledged unconditionally, even when interrupts are disabled (DI state). An NMI
is not subject to priority control and takes precedence over all other interrupts.
The following two non-maskable interrupt requests are available in the V850/SC1, V850/SC2, and V850/SC3.
• NMI pin input (NMI)
• Non-maskable watchdog timer interrupt request (INTWDT)
When the valid edge specified by the rising edge specification register 0 (EGP0) and falling edge specification
register 0 (EGN0) is detected at the NMI pin, an interrupt occurs.
INTWDT functions as the non-maskable interrupt (INTWDT) only when the WDTM4 bit of the watchdog timer
mode register (WDTM) is set to 1.
While the service routine of a non-maskable interrupt is being executed (PSW.NP = 1), the acknowledgement of
another non-maskable interrupt request is held pending. The pending NMI is acknowledged when PSW.NP is
cleared to 0 after the original service routine of the non-maskable interrupt under execution has been terminated (by
the RETI instruction). Note that if two or more NMI requests are input during the execution of the service routine for
an NMI, only are NMI will be acknowledged after PSW.NP is cleared to 0.
Caution Do not clear PSW.NP to 0 using the LDSR instruction during non-maskable interrupt servicing.
If PSW. NP is cleared to 0, subsequent interrupts cannot be acknowledged correctly.
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
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