Maskable Interrupts; Operation - NEC V850/SA1 mPD703015 Preliminary User's Manual

5.3 Maskable Interrupts

Maskable interrupt requests can be masked by interrupt control registers. The V850/SA1 has 30 maskable inter-
rupt sources.
If two or more maskable interrupt requests are generated at the same time, they are accepted according to the
default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt con-
trol registers, allowing programmable priority control.
When an interrupt request has been acknowledged, the acceptance of other maskable interrupts is disabled and
the interrupt disabled (DI) status is set.
When the EI instruction is executed in an interrupt processing routine, the interrupt enabled (EI) status is set which
enables interrupts having a higher priority to immediately interrupt the current service routine in progress. Note that
only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested.
To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the
EI instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI
instruction.
The WDTM4 bit of the watchdog timer mode register (WDTM) is set to 0, and the watchdog timer overflow inter-
rupt functions as a maskable interrupt (INTWDTM).

5.3.1 Operation

If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler rou-
tine:
(1) Saves the restored PC to EIPC.
(2) Saves the current PSW to EIPSW.
(3) Writes an exception code to the lower half-word of ECR (EICC).
(4) Sets the ID bit of PSW and clears the EP bit.
(5) Loads the corresponding handler address to the PC, and transfers control.
The INT input masked by INTC and the INT input that occurs during the other interrupt processing (when PSW.NP
= 1 or PSW.ID = 1) are internally pended. When the interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0
by using the RETI and LDSR instructions, the pending INT inputs the new maskable interrupt processing.
Figure 5-6 illustrates how the maskable interrupts are processed.
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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION