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7.2 Non-Maskable Interrupts
A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the
interrupt disabled (DI) status.
Non-maskable interrupts of V850E/CA1 / ATOMIC are available for the following two requests:
• NMI pin input (NMIVC)
• Non-maskable watchdog timer interrupt request (NMIWDT)
When the valid edge specified by bits EDN1, EDN0 of the voltage comparator mode register (VCMPM)
is detected on the NMI pin, or the comparator output, depending on the NSOCE bit of voltage compara-
tor mode register (VCMPM), the interrupt occurs.
The watchdog timer interrupt request (NMIWDT) is only effective as non-maskable interrupt if the
WDTM bit of the watchdog timer mode register (WDTM) is set 0.
If multiple non-maskable interrupts are generated at the same time, the highest priority servicing is exe-
cuted according to the following priority order (the lower priority interrupt is ignored):
NMIWDT > NMIVC
Note that if an NMIVC or NMIWDT request is generated while NMIVC is being serviced, the service is
executed as follows.
(1)
If an NMIVC is generated while NMIVC is being serviced
The new NMIVC request is held pending regardless of the value of the PSW.NP bit. The pending
NMIVC request is acknowledged after servicing of the current NMIVC request has finished (after
execution of the RETI instruction).
(2)
If an NMIWDT request is generated while NMIVC is being serviced
If the PSW.NP bit remains set (1) while NMIVC is being serviced, the new NMIWDT request is held
pending. The pending NMIWDT request is acknowledge after servicing of the current NMIVC
request has finished (after execution of the RETI instruction).
If the PSW.NP bit is cleared (0) while NMIVC is being serviced, the newly generated NMIWDT
request is executed (NMIVC servicing is halted).
Remark: PSW.NP: The NP bit of the PSW register.
Cautions: 1. Although the values of the PC and PSW are saved to an NMI status save register
(FEPC, FEPSW) when a non-maskable interrupt request is generated, only the
NMIVC can be restored by the RETI instruction at this time. Because NMIWDT can-
not be restored by the RETI instruction, the system must be reset after servicing
this interrupt.
2. If PSW.NP is cleared to 0 by the LDSR instruction during non-maskable interrupt
servicing, a NMIVC interrupt afterwards cannot be acknowledged correctly.
Chapter 7 Interrupt/Exception Processing Function
Preliminary User's Manual U14913EE1V0UM00
187
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