Non-Maskable Interrupts - NEC V850ES/KE1+ User Manual

32-bit single-chip microcontrollers
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION

17.2 Non-Maskable Interrupts

Non-maskable interrupt request signals are acknowledged unconditionally, even when interrupts are disabled (DI
state). Non-maskable interrupts (NMI) are not subject to priority control and take precedence over all other interrupt
request signals.
The following three types of non-maskable interrupt request signals are available in the V850ES/KE1+.
• NMI pin input (NMI)
• Non-maskable interrupt request signal (INTWDT1) due to overflow of watchdog timer 1
• Non-maskable interrupt request signal (INTWDT2) due to overflow of watchdog timer 2
There are four choices for the valid edge of an NMI pin, namely: rising edge, falling edge, both edges, and no edge
detection.
The non-maskable interrupt request signal (INTWDT1) due to overflow of watchdog timer 1 functions by setting the
WDTM1.WDTM14 and WDTM1.WDTM13 bits to 10.
The non-maskable interrupt request signal (INTWDT2) due to overflow of watchdog timer 2 functions by setting the
WDTM2.WDM21 and WDTM2.WDM20 bits to 01.
When two or more non-maskable interrupts occur simultaneously, they are processed in a sequence determined
by the following priority order (the interrupt request signals with low priority level are ignored).
INTWDT2 > INTWDT1 > NMI
If during NMI processing, an NMI, INTWDT1, or INTWDT2 request signal newly occurs, processing is performed as
follows.
(1) If an NMI request signal newly occurs during NMI processing
The new NMI request signal is held pending regardless of the value of the PSW.NP bit. The NMI request
signal held pending is acknowledged upon completion of processing of the NMI currently being executed
(following RETI instruction execution).
(2) If an INTWDT1 request signal newly occurs during NMI processing
If the NP bit remains set (to 1) during NMI processing, the new INTWDT1 request signal is held pending. The
INTWDT1 request signal held pending is acknowledged upon completion of processing of the NMI currently
being executed (following RETI instruction execution).
If the NP bit is cleared (to 0) during NMI processing, a newly generated INTWDT1 request signal is executed
(NMI processing is interrupted).
(3) If an INTWDT2 request signal newly occurs during NMI processing
A newly generated INTWDT2 request signal is executed regardless of the value of the NP bit (NMI processing
is interrupted).
Caution For non-maskable interrupt servicing from non-maskable interrupt request signals (INTWDT1,
INTWDT2), refer to 17.10 Cautions.
534
User's Manual U16896EJ2V0UD

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