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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.3 Maskable Interrupts
Maskable interrupt requests can be masked by interrupt control registers. The V854 has 31 maskable interrupt
sources.
If two or more maskable interrupt requests are generated at the same time, they are accepted according to the
default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control
registers, allowing programmable priority control.
When an interrupt request has been acknowledged, the acceptance of other maskable interrupts is disabled and
the interrupt disabled (DI) status is set.
When the EI instruction is executed in an interrupt processing routine, the interrupt enabled (EI) status is set which
enables interrupts having a higher priority to immediately interrupt the current service routine in progress. Note that
only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested.
To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the
EI instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI
instruction.
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