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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.2.2 Restore
Execution is restored from the non-maskable interrupt processing by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
(1) Restores the values of PC and PSW from FEPC and FEPSW, respectively, because the EP bit of PSW is 0
and the NP bit of PSW is 1.
(2) Transfers control back to the restored PC address and PSW status.
Figure 5-3 illustrates how the RETI instruction is processed.
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Caution
When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during the non-
maskable interrupt process, in order to restore the PC and PSW correctly during recovery
by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using
the LDSR instruction immediately before the RETI instruction.
Remark
The solid line shows the CPU processing flow.
Figure 5-3. RETI Instruction Processing
RETI instruction
PSW. EP
0
PSW. NP
0
← EIPC
PC
← EIPSW
PSW
Original processing restored
User's Manual U11969EJ3V0UM00
1
← FEPC
PC
← FEPSW
PSW
105
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