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CLOCK
V SS
ENABLE
A
V DD
S1
RESET
B
V SS
S1
CLOCK C out
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
500 µF
f c
PULSE
GENERATOR
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are se-
quential within each stage and from stage to stage, with no dead time (except propagation delay).
CLOCK
CE
Q0 Q1
CLOCK
MOTOROLA CMOS LOGIC DATA
V DD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
EXTERNAL
POWER
SUPPLY
V SS
V DD
0.01 µF
I D
CERAMIC
Q0
Q1
CLOCK
Q2
ENABLE
Q3
Q4
RESET
Q5
Q6
Q7
CLOCK
Q8
Q9
C out
V SS
Figure 2. Typical Power Dissipation Test Circuit
APPLICATIONS INFORMATION
RESET
CLOCK
MC14017B
CE
Q8 Q9
Q0Q1
9 DECODED
OUTPUTS
FIRST STAGE
INTERMEDIATE STAGES
Figure 3. Counter Expansion
V out
Decode
Outputs
I D
Carry
V GS =
V DS =
C L
C L
C L
C L
C L
C L
RESET
MC14017B
Q8 Q9
8 DECODED
OUTPUTS
Output
Output
Sink Drive
Source Drive
Clock to
desired
(S1 to A)
outputs
(S1 to B)
Clock to 5
thru 9
S1 to A
(S1 to B)
V DD
– V DD
V out
V out – V DD
C L
C L
C L
C L
C L
RESET
CLOCK
MC14017B
CE
Q1
Q8 Q9
8 DECODED
OUTPUTS
LAST STAGE
MC14017B
6–57
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