Motorola CMOS Logic Manual page 406

V DD V DD
P1
R X
2 (14)
C X
(15)
1
N1
V SS
4 (12)
A
5 (11)
B
3 (13)
RESET
500 pF
R X
V SS C X
V in
A
B
RESET
A
B
RESET
V DD
R X
C X
V SS
C X /R X
A
PULSE
GENERATOR
B
RESET
PULSE
GENERATOR
A
B
PULSE
GENERATOR
RESET
MC14538B
6–368
+
C1
–
V ref1
V ref2
ENABLE
CONTROL
Figure 1. Logic Diagram
(1/2 of DevIce Shown)
V DD
0.1 µF
I D
CERAMIC
R X
C X
V SS
C X /R X
Q
C L
Q
C L
Q
C L
Q
C L
V SS
Figure 2. Power Dissipation Test Circuit and Waveforms
R X
* C L = 50 pF
C X
V SS
Q
C L
Q
C L
Q
C L
Q
C L
V SS
Figure 3. Switching Test Circuit
ENABLE
+
C2
–
Q R Q R
RESET LATCH
S S R
20 ns
90%
10%
V in
Characteristics
t PLH , t PHL , t TLH , t THL ,
T, t WH , t WL
t PLH , t PHL , t TLH , t THL ,
T, t WH , t WL
t PLH(R) , t PHL(R) ,
t WH , t WL
* Includes capacitance of probes,
wiring, and fixture parasitic.
NOTE: Switching test waveforms
for PG1, PG2, PG3 are shown
In Figure 4.
R Q 6 (10)
OUTPUT
LATCH
S Q 7 (9)
NOTE: Pins 1, 8 and 15 must
be externally grounded
20 ns
V DD
0 V
INPUT CONNECTIONS
Reset A
V DD PG1
V DD V SS
PG3 PG1
PG1 =
PG2 =
PG3 =
MOTOROLA CMOS LOGIC DATA
B
V DD
PG2
PG2