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PULSE
GEN.
PULSE
NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8–Bypass,
A, B, C, and D inputs, and the clock input period. A 2 n frequency division (where n = the
number of stages selected from the truth table) is obtainable at Decode Out. A 2 0 –divided
output of IN 1 can be obtained at OUT 1 and OUT 2 .
Figure 9. Time Interval Configuration Using an External Clock, Set,
MC14536B
6–362
GEN.
CLOCK
IN 1
SET
CLOCK INH
DECODE OUT
POWER UP
and Clock Inhibit Functions
(Divide–by–2 Configured)
+V
16
6
V DD
8–BYPASS
9
A
OUT 1
10
B
11
C
12
D
2
RESET
OUT 2
14
OSC INH
15
MONO–IN
1
SET
7
CLOCK INH
3
DECODE OUT
IN 1
V SS
8
MOTOROLA CMOS LOGIC DATA
4
5
13
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