Motorola CMOS Logic Manual page 384

D15 D14 D13 D12 D11 D10 D9
D7 D6 D5
V DD E in
GS
Q3
DIGITAL TO ANALOG CONVERSION
The digital eight–bit word to be converted is applied to
the inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at V DD = 10 V) is applied to the MC14520B.
A compromise between I bias for the MC1710 and ∆R
between N and P–channel outputs gives a value of R of
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms, [
0.03 µF). The analog 3.0 dB bandwidth would then be
C
dc to 1.0 kHz.
ANALOG TO DIGITAL CONVERSION
An analog signal is applied to the analog input of the
MC1710. A digital eight–bit word known to represent a digi-
tized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is increm-
ented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.
MC14532B
6–346
D8
D4 D3 D2 D1 D0
E out
Q2 Q1 Q0
Q2 Q1 Q0
Figure 4. Two MC14532B's Cascaded for 4–Bit Output
CLOCK
Figure 5. Digital to Analog and Analog to Digital Converter
D7 D6 D5 D4 D3 D2
D7 D6 D5 D4 D3 D2
E in
Q2 Q1
3/4 MC14071B
V DD
INPUT
C E
1/2 MC14520B
Q1 Q2 Q3
D0 D1 D2 D3 D4 D5 D6 D7
V DD E in
Q2 Q1
STOP
WORD
INCREMENTATION
MOTOROLA CMOS LOGIC DATA
D1 D0
D1 D0
E out = "1"
E out
WITH D in = "0"
Q0
V SS
R C E
1/2 MC14520B
Q4 Q1 Q2 Q3
DIGITAL INPUT/OUTPUT
8–BIT WORD
TO BE CONVERTED
Q0
X7 X6 X5 X4 X3 X2 X1 X0
A
B
MC14512
C
Z
MC1710
R
ANALOG
OUTPUT
C
ANALOG
INPUT
R
Q4