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CLOCK
CARRY IN
UP/DOWN
BINARY/DECADE
PE
P0
P1
P2
P3
Q0
Q1
Q2
Q3
CARRY OUT
COUNT 0
Q3 Q2 Q1 Q0
C out
MC14029B
U/D
MSD
B/D
P3 P2 P1 P0 CLK
V DD
"1"
INPUT
CLOCK
CLOCK
C out 1 (LSD)
C out 2
C out 3 (MSD)
PE
COUNT
Figure 3. Divide by N BCD Down Counter and Timing Diagram
MC14029B
6–90
TIMING DIAGRAM
1
2
3
4
5
6
7
8
Q3 Q2 Q1 Q0
C in
C out
U/D
MC14029B
PE
B/D
P3 P2 P1 P0 CLK
V DD
"2"
(Shown for N = 123)
9
8
7
6
5
4
3
2
Q3 Q2 Q1 Q0
C in
C out
MC14029B
U/D
LSD
PE
B/D
P3 P2 P1 P0 CLK
"3"
^
* t W
900 ns @ V DD = 5 V
1
0
0
9
6
7
0
C in
PE
OUTPUT
V DD
V DD
MOTOROLA CMOS LOGIC DATA
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