Motorola CMOS Logic Manual page 401

PULSE
GEN.
CLOCK
IN 1
RESET
DECODE OUT
POWER UP
NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
input low enables the chip's internal counters. After Reset goes low, the 2 n /2 negative transition of the clock input causes
Decode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2 n x (the clock
period) intervals where n = the number of stages selected from the truth table.
Figure 10. Time Interval Configuration Using an External Clock, Reset,
MOTOROLA CMOS LOGIC DATA
6
8–BYPASS
R X
9
A
10
B
11
C
12
D
2
RESET
1
SET
7
CLOCK INH
15
MONO–IN
14
CLOCK INH
3
IN 1
C X
*t w
and Output Monostable to Achieve a Pulse Output
(Divide–by–4 Configured)
+V
16
V DD
4
OUT 1
5
OUT 2
13
DECODE OUT
V SS
8
*t w
t w in µsec
R X in kΩ
C X in pF
.00247 R X C X 0.85
MC14536B
6–363