Motorola CMOS Logic Manual page 535

V DD
SEE
PULSE
TEST
GENERATOR
TABLE
V SS
MC14581B
C n C n+4 C n C n+4
16–BIT ALU, RIPPLE CARRY
MC14581B
C n C n
G P G P
G0 P0 C n+x G1 P1 C n+y
C n
MC14582B
16–BIT ALU, TWO LEVEL LOOK–AHEAD
C n C n
G P G P
G0 P0 C n+x G1 P1 C n+y
C n
MC14582B
C n C n+4 C n+4
C n C n
G P G P
G0 P0 C n+x G1 P1 C n+y
C n
MC14582B
A AND B INPUTS AND F OUTPUTS ARE NOT SHOWN (MC14581B).
MOTOROLA CMOS LOGIC DATA
V out
C in
C n+x
G0
G1
C n+y
C L
G2
C n+z
G3
P0
P
P1
P2
G
P3
Figure 4. Switching Time Test Circuit and Waveforms
TYPICAL APPLICATIONS
C n C n+4 C n C n+4
C n C n+4
C n
G P G P
G2 P2 C n+z G3 P3
G P
MC14581B
C n C n+4
C n C n
G P G P G P
G2 P2 C n+z G3 P3 G0 P0 C n+x
C n
G P
32–BIT ALU, TWO LEVEL LOOK–AHEAD OVER 16–BIT GROUPS
MC14581B
C n C n C n
G P G P G P
G0 P0 C n+x G1 P1 C n+y G2 P2 C n+z
C n
MC14582B
COMBINED TWO–LEVEL LOOK–AHEAD AND RIPPLE CARRY ALU
MC14581B
C n C n C n
G P G P G P
G2 P2 C n+z G3 P3 G0 P0 C n+x
C n
G P
G0 P0 C n+x
C n
64–BIT ALU, FULL–CARRY LOOK–AHEAD IN THREE LEVELS.
TEST TABLE
AC Paths
Input Output
P0 P
G0 G
C n C n+x , C n+y ,
C n+z
20 ns
90%
V in
50%
t PLH
V out
t TLH
C n C n+4
C n C n
G P G P G P
G1 P1 C n+y G2 P2 C n+z G3 P3
MC14582B
G P
C n C n+4
C n C n+4 C n
G P G P
G3 P3 G0 P0 C n+x
C n
G P
C n+4
C n C n C n
G P G P G P
G1 P1 C n+y G2 P2 C n+z G3 P3
MC14582B
G P
G1 P1
MC14582B
DC Data
To V SS To V DD
Remaining G's
P's, C n
P's, C n Remaining
G's
P's G's
20 ns
V DD
10%
V SS
t PHL
V OH
V OL
t THL
C n
G P
G1 P1 C n+y
MC14582B
C n
G P
G0 P0 C n+x
C n
MC14582B
C n+y
MC14582B
6–497