Motorola CMOS Logic Manual page 38

V DD
N+
N–CHANNEL OUTPUT
V SS
V SS
P–WELL RESISTANCE
MOTOROLA CMOS LOGIC DATA
P–CHANNEL
P–CHANNEL
V DD
OUTPUT
Ç Ç Ç
FIELD OXIDE
P+ P+
N – SUBSTRATE
Figure 10. CMOS Wafer Cross Section
Q1
N+ N+ N–
P–
Figure 11. Latch Up Circuit Schematic
N–CHANNEL
INPUT
N–CHANNEL
OUTPUT
OUTPUT
Ç Ç
FIELD OXIDE
N+ N+
P – WELL
N–SUBSTRATE RESISTANCE
N–
P+
P–
P+
Q2
V SS
FIELD OXIDE
P+
V DD
V DD
P–CHANNEL OUTPUT
CHAPTER 5
5–7