Motorola CMOS Logic Manual page 203

INPUT RISE AND FALL 20 ns
90%
INPUT
D
50%
INFORMATION
10%
t h
t su
50%
t WH
f cl
t PLH
90%
Q OUTPUT
10%
t TLH
RESET = 0
DATA DISABLE A AND B = 0
OUTPUT DISABLE A AND B = 0
Figure 1. Timing Diagram
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A 1
OUTPUT DISABLE B 2
D0 14
DATA DISABLE A 9
DATA DISABLE B 10
D1 13
CLOCK 7
D2 12
D3 11
RESET 15
MOTOROLA CMOS LOGIC DATA
V DD
V SS
t h
t su
20 ns
V DD
90%
10%
V SS
t WL
t PHL
V OH
50%
V OL
t THL
D Q
C
Q
R
D Q
C
Q
R
D Q
C
Q
R
D Q
C
Q
R
20 ns
OUTPUT
90%
DISABLE
50%
50%
10%
A OR B
t PLZ
ANY Q
90%
OUTPUT
10%
t PHZ
90%
ANY Q
10%
OUTPUT
OUTPUTS OUTPUTS
CONNECTED DISCONNECTED
ANY Q
OUTPUT
OTHER
R L = 1 kΩ
INPUTS
MC14076B
OUTPUT C L
DISABLE
A OR B
Figure 2. Three–State Propagation Delay
Waveshape and Circuit
{
OUTPUT
DISABLE
3 Q0
V SS
4 Q1
5 Q2
6 Q3
20 ns
V DD
V SS
t PZL
V OH
2.5 V @ V DD = 5 V,
10 V, AND 15 V
t PZH
2 V @ V DD = 5 V
6 V @ V DD = 10 V
10 V @ V DD = 15 V
V OL
OUTPUTS
CONNECTED
V DD FOR t PLZ AND t PZL
V SS FOR t PHZ AND t PZH
PIN ASSIGNMENT
A 1 16 V DD
B 2 15 R
Q0 3 14 D0
Q1 4 13 D1
Q2 5 12 D2
Q3 6 11 D3
}
C 7 10 B
DATA
DISABLE
8 9 A
MC14076B
6–165