Advertisement
SERIAL DATA INPUT
PARALLEL/SERIAL P/S
ASYN/SYN A/S
The MC14034B is composed of eight register cells con-
nected in cascade with additional control logic. Each register
cell is composed of one "D" master–slave flip–flop with sepa-
rate internal clocks, and two data transfer gates allowing the
data to be transferred bi–directionally from bus A to bus B
and from bus B to bus A, and to be memorized. Besides the
single phase clock and the serial data inputs, the control log-
ic provides four other features:
A Enable Input — When high, this input enables the bus A
data lines.
A/B Input (Data A or B) — This input controls the direc-
tion of data flow: when high, the data flows from bus A to bus
A ENABLE
9
A/B 11
SERIAL DATA 10
PARALLEL SERIAL 13
ASYN/SYN 14
CLOCK 15
MC14034B
6–100
EXPANDED BLOCK DIAGRAM
A1
ENABLE A
A/B
CONTROL
LOGIC
CLOCK
B1
OPERATING CHARACTERISTICS
LOGIC DIAGRAM
*D FLIP FLOP
C M
DATA
A2
A3
A4
A5
8–BIT REGISTER
B2
B3
B4
B5
B6
DATA
B; when low, the data flows from bus B to bus A.
P/S Input (Parallel/Serial) — This input controls the data
input mode (parallel or serial). When high, the data is trans-
ferred to the register in a parallel asynchronous mode or a
parallel synchronous mode (positive clock transition). When
low, the data is entered into the register in a serial synchro-
nous mode (positive clock transition).
A/S Input (Asynchronous/Synchronous to the Clock)
— When this input is high, the data is transferred indepen-
dently from the clock rate; when low, the clock is enabled and
the data is transferred synchronously.
A1
A2
A3
A4
16
17
18
19
V DD
6 STAGES
(SAME AS
STAGE 1)
C S
V DD
7
6
5
8
B2
B3
B4
B1
MOTOROLA CMOS LOGIC DATA
A6
A7
A8
B7
B8
A5
A6
A7
20
21
22
V DD
*D
FLIP–
FLOP
D
Q
C M C S
4
3
2
B5
B6
B7
A8
23
1
B8
Advertisement
