Advertisement
Table 4. Mode Controls
P7
P6
P5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
0
2 7
2 6
2 5
128
64
32
Counter #2
BCD
X = No Output (Always Low)
MOTOROLA CMOS LOGIC DATA
(CTL 1 = Low, CTL 2 = High, Cascade Feedback = High)
Preset Values
P4
P3
P2
P1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
2 4
2 3
2 2
2 1
16
8
4
2
Counter #1
Binary
Divide Ratio
Zero
Detect
P0
Q
0
160
160
1
X
X
0
2
X
1
3
X
X
X
X
1
15
X
0
16
X
X
X
X
1
31
X
0
32
X
X
X
X
0
48
X
0
64
X
0
80
X
0
112
X
0
128
128
0
144
144
1
159
159
2 0
1
Comments
Max Count
Illegal State
Min Count
Q Output Active
Bit Value
Counting
Sequence
MC14569B
6–477
Advertisement
