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Motorola CMOS Logic Manual page 557

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NOTE: This data sheet has a new look — the technical content has not changed.
where R(t) = Reaction rate as a function of time and
temperature
R 0 = A constant
t
= Time
θ
= Activation energy in electron volts
k
= Boltzman's constant
T
= Temperature in degrees Kelvin
To provide time–temperature equivalents this equation is
applied to failure rate calculations in the form:
t = t 0 e θ/kT
where t = time
t 0 = A constant
The Arrhenius equation essentially states that reaction
rate increases exponentially with temperature. This pro-
duces a straight line when plotted in log–linear paper with a
slope expressed by Θ. Θ may be physically interpreted as
the energy threshold of a particular reaction or failure mecha-
nism. The activation energy exhibited by semiconductors
varies from about 0.3 eV. Although the relationships do not
prohibit devices from having poor failure rates and high
activation energies, good performance usually does not
imply a high Θ. Studies by Bell Telephone Laboratories have
indicated that an overall Θ for semiconductors is 1.0 eV. This
value has been accepted by the Rome Air Development
Command for time–temperature acceleration in powered
burn–in. Data taken by Motorola on Integrated Circuits have
verified this number and it is therefore applied as our stan-
dard time–temperature regression for extrapolation of high
temperature failure rates to temperatures at which the
devices will be used (Figure 3). For Discrete products, 0.7 eV
is generally applied.
To accomplish this, the time in device hours (t1) and tem-
perature (T1) of the test are plotted as point P1. A vertical
line is drawn at the temperature of interest (T2) and a line
with a 1.0 eV slope is drawn through point P1.
Its intersection with the vertical line defines point P2, and
determines the number of equivalent device hours (t2). This
number may then be used with the x 2 formula to determine
the failure rate at the temperature of interest. Assuming T1 of
125 _ C at t1 of 10,000 hours, a t2 of 7.8 million hours results
at a T2 of 50 _ C. If one reject results in the 10,000 device
hours of testing at 125 _ C, the failure rate at that temperature
will be 0.1%/1,000 hours using a 60% confidence level. One
reject at the equivalent 7.8 million device hours at 50 _ C will
result in a 0.0008%/1,000 hour failure rate, as illustrated in
Figure 4.
Three parameters determine the failure rate quoted by the
manufacturer: the failure rate at the test temperature, the
activation energy employed, and the difference between the
test temperature and the temperature of the quoted λ. A term
often used in this manipulation is the "acceleration factor"
which is simply the equivalent device hours at the lower tem-
perature divided by the actual test device hours.
Every device will eventually fail, but with the present tech-
niques in Semiconductor design and applications, the wear-
out phase is extended far beyond the lifetime required.
During wearout, as in infant mortality, the failure rate is
changing rapidly and therefore loses its value. The parame-
ter used to describe performance in this area is "Median Life"
and is the point at which 50% of the devices have failed.
There are currently only few significant wearout mecha-
nisms: electromigration of circuit metallization, electrolytic
CHAPTER 7
7–3
corrosion in plastic devices and metal fatigue for Power
devices.
1.2
1.6
2.0
1000 k
100 k
10 k
t2
1.0 k
100
10
t1
1.0
0.1
500
200
TEMPERATURE ( C)
Figure 3. Normalized Time–Temperature
Regressions for Various Activation Energy Values
100 k
1.2
1.6
2.0
100
10
1.0
λ2
0.01
λ1
0.0001
0.00001
500
200
TEMPERATURE ( C)
Figure 4. Failure Rate
For increased flexibility in working with a broad range of
device hours, the time–temperature regression lines have
been normalized to 500 _ C and the time scale omitted, per-
mitting the user to define the scale based on his own require-
ments.
MOTOROLA CMOS LOGIC DATA
2.4
2.8
3.2
3.6
P2
P1
1.0 eV
SLOPE
T1
T2
100
50
0
2.4
2.8
3.2
3.6
100
50
0

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