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For input voltages outside of the recommended operating
range, the CMOS input is modeled as in Figure 9. The
resistor–diode protection network allows the user greater
freedom when designing a worst case system. The device
inputs are guaranteed to withstand voltages from V SS – 0.5 V
to V DD + 0.5 V and a maximum current of 10 mA. With the
above input ratings, most designs will require no special
terminations or design considerations.
D1
1.5 k
Figure 8. Input Model for V in > V DD or V in < V SS
Other specifications that should be noted are the maxi-
mum input rise and fall times. Figure 10 shows the
oscillations that may result from exceeding the 15 µs
maximum rise and fall time at V DD = 5.0 V, 5 µs at 10 V, or
4 µs at 15 V. As the voltage passes through the switching
threshold region with a slow rise time, any noise that is on the
input is amplified, and passed through to the output, causing
oscillations. The oscillation may have a low enough fre-
quency to cause succeeding stages to switch, giving
unexpected results. If input rise or fall times are expected to
exceed 15 µs at 5.0 V, 5 µs at 10 V, or 4 µs at 15 V,
Schmitt–trigger devices such as the MC14093B, MC14583B,
MC14584B, MC14106B, HC14, or HC132 are recommended
for squaring–up these slow transitions.
V DD
V in
V SS
V OH
V out
V OL
Figure 9. Maximum Rise and Fall Time Violations
OUTPUTS
All CMOS B–Series outputs are buffered to insure consis-
tent output voltage and current performance. All buffered out-
puts have guaranteed output voltages of V OL = 0.05 V and
V OH = V DD – 0.05 V for V in = V DD or V SS and l out = 0 µA. The
output drives for all buffered CMOS devices are such that
1 LSTTL load can be driven across the full temperature
range.
CHAPTER 5
5–6
7.5 pF
D2
CMOS outputs are limited to externally forced output
v
voltages of V SS – 0.5 V
voltages are forced outside of this range, a silicon controlled
rectifier (SCR) formed by parasitic transistors can be
triggered, causing the device to latch up. For more informa-
tion on this, see the explanation of CMOS Latch Up in this
section.
The maximum rated output current for most outputs is
10 mA. The output short–circuit currents of these devices
typically exceed these limits. Care must be taken not to ex-
ceed the maximum ratings found on every data sheet.
For applications that require driving high capacitive loads
where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
prevent it.
Figure 11 shows the cross–section of a typical CMOS in-
verter and Figure 12 shows the parasitic bipolar devices. The
circuit formed by the parasitic transistors and resistors is the
basic configuration of a silicon controlled rectifier, or SCR. In
the latch up condition, transistors Q1 and Q2 are turned ON,
each providing the base current necessary for the other to
remain in saturation, thereby latching the devices in the ON
state. Unlike a conventional SCR, where the device is turned
ON by applying a voltage to the base of the NPN transistor,
the parasitic SCR is turned ON by applying a voltage to the
emitter of either transistor. The two emitters that trigger the
SCR are the same point, the CMOS output. Therefore, to
latch up the CMOS device, the output voltage must be great-
er than V DD + 0.5 V or less than V SS – 0.5 V and have suffi-
cient current to trigger the SCR. The latch–up mechanism is
similar for the inputs.
Once a CMOS device is latched up, if the supply current is
not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
1. Insure that inputs and outputs are limited to the maxi-
mum rated values, as follows:
v
– 0.5 V V in or V out
v
V DD + 0.5 V (referenced to V SS )
|I in or I out |
10 mA (unless otherwise indicated on the
data sheet)
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
to limit the expected worst case current to the maximum
rating of 10 mA. (See Figure 2).
3. Sequence power supplies so that the inputs or outputs
of CMOS devices are not active before the supply pins
are powered up (e.g., recessed edge connectors and/
or series resistors may be used in plug–in board ap-
plications).
4. Voltage regulating or filtering should be used in board
design and layout to insure that power–supply lines are
free of excessive noise.
5. Limit the available power supply current to the devices
that are subject to latch–up conditions. This can be ac-
complished with the power supply filtering network or
with a current–limiting regulator.
MOTOROLA CMOS LOGIC DATA
v
V out
V DD + 0.5 V. When
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