Motorola CMOS Logic Manual page 525

V DD
WE
PULSE
W0
GENERATOR
W1
1
R0 A
R1 A
R0 B
PULSE R1 B
GENERATOR
C
2
D0
D1
PULSE D2
GENERATOR D3
3
V SS
Figure 2. Power Dissipation Test Circuit and Waveforms (3–State Inputs are High)
t w (H)
CLOCK
50%
t su
ADDRESS DATA 50%
t PLH , t PHL
Q
t TLH , t THL
Figure 3.
50%
CLOCK
t su
50%
WE
Figure 5.
MOTOROLA CMOS LOGIC DATA
I DD
Q0 A
Q1 A
Q2 A
Q3 A
Q0 B
C L
Q1 B
C L
Q2 B
C L
Q3 B
C L
t w (L)
V DD
V SS
t h
V DD
V SS
V OH
90%
50%
10%
V OL
V DD
50%
V SS
t rem
V DD
50%
V SS
1 kΩ
Q
DEVICE
UNDER
C L
TEST
Figure 7. Test Circuit
C L
C L
P.G. 1
C L
C L
P.G. 2
P.G. 3
OUTPUT
Q n A, B
3–STATE
50%
A OR B
t PHZ
90%
Q A
t PZL
Q B
10%
Figure 4.
DEVICE
UNDER
TEST
Figure 6. Test Circuit
CONNECT TO V CC WHEN TESTING t PLZ AND t PZL
CONNECT TO GND WHEN TESTING t PHZ AND t PZH
REPETITIVE WAVEFORMS
V DD
50%
V SS
t PZH
V OH
10%
V OL
t PZL
V OH
90%
V OL
Q
C L
MC14580B
6–487