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CARRY IN OR
UP/DOWN
CLOCK
PRESET ENABLE
Q 0 OR CARRY OUT
RESET
INPUTS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) — This active–low input is used when
Cascading stages. Carry In is usually connected to Carry
Out of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) — Binary data is incremented or decrem-
ented, depending on the direction of count, on the positive
transition of this input.
OUTPUTS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) —
Binary data is present on these outputs with Q0 correspond-
ing to the least significant bit.
Carry Out, (Pin 7) — Used when cascading stages, Carry
Out is usually connected to Carry In of the next stage. This
MC14516B
6–284
t su
t h
50%
50%
t w(H)
t w(H)
CARRY OUT ONLY
90%
10%
t THL
t PLH
50%
t w
Figure 2. Switching Time Waveforms
PIN DESCRIPTIONS
t rem
1
f cl
90%
10%
t PHL
t rem
synchronous output is active low and may also be used to
indicate terminal count.
CONTROLS
PE, Preset Enable, (Pin 1) — Asynchronously loads data
on the Preset Inputs. This pin is active high and inhibits the
clock when high.
R, Reset, (Pin 9) — Asynchronously resets the Q out–
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) — Controls the direction of count, high
for up count, low for down count.
SUPPLY PINS
V SS , Negative Supply Voltage, (Pin 8) — This pin is
usually connected to ground.
V DD , Positive Supply Voltage, (Pin 16) — This pin is
connected to a positive supply voltage ranging from 3.0 volts
to 18.0 volts.
MOTOROLA CMOS LOGIC DATA
V DD
V SS
V DD
V SS
V DD
V SS
t TLH
V OH
V OL
t PLH
V DD
V SS
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