Advertisement
PULSE
GENERATOR
9
CLOCK
CLEAR
13
SET TO NINE
MOTOROLA CMOS LOGIC DATA
V DD
0.01 µF
500
I D
pF
CERAMIC
V DD
S
C ASC
E out
E in
CLOCK
OUT
ST
A
OUT
B
C
C L
D
"9"
C L
CLEAR
C L
V SS
Figure 3. Power Dissipation Test Circuit and Waveform
LOGIC DIAGRAM
D C
ENABLE IN
3
2 15 14
11
Q
T
C
a
Q
R
T
Q
C
b
R
S
T
Q
C
c
Q
R
S
Q
T
d
C
Q
R
4
90%
CLOCK
50%
10%
VARIABLE WIDTH
C L
50% DUTY CYCLE
B A
STROBE CASCADE
10
R1
R2
R3
R4
20 ns
20 ns
V DD
V SS
12
6 OUT
5 OUT
V DD = PIN 16
V SS = PIN 8
1 "9"
7 ENABLE OUT
MC14527B
6–319
Advertisement
