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Externally Controlled 6–Bit ADC (Figure 2)
Several features are shown in this application:
Shortening of the register to six bits by feeding the seventh
output bit into the FF input.
Continuous conversion, if a continuous signal is applied to
SC.
Externally controlled updating (the start pulse must be
shorter than the conversion cycle).
The EOC output indicating that the parallel data are valid
and that the serial output is complete.
Continuously Cycling 8–Bit ADC (Figure 3)
This ADC is running continuously because the EOC signal
is fed back to the SC input, immediately initiating a new cycle
on the next clock pulse.
MOTOROLA CMOS LOGIC DATA
TYPICAL APPLICATIONS
Continuously Cycling 12–Bit ADC (Figure 4)
has a capability of handling only an eight–bit word, two must
be cascaded to make an ADC with more than eight bits.
SAR must have a stable resettable state to remain in while
awaiting a subsequent start signal. However, the first stage
must not have a stable resettable state while recycling, be-
cause during switch–on or due to outside influences, the first
stage has entered a reset state, the entire ADC will remain in
a stable non–functional condition.
well as the parallel outputs are updated every thirteenth
clock pulse. The EOC pulse indicates the completion of
C
SC
MC14559B
Q7 Q6
Q5
Q4 Q3
Q2
TO DAC
Figure 2. Externally Controlled 6–Bit ADC
C
SC
MC14559B
Q7 Q6
Q5
Q4 Q3
Q2
TO DAC
Figure 3. Continuously Cycling 8–Bit ADC
Because each successive approximation register (SAR)
When it is necessary to cascade two SAR's, the second
This 12–bit ADC is continuously recycling. The serial as
S out
Q1
Q0
FF
EOC
S out
Q1
Q0
FF
EOC
MC14549B MC14559B
6–403
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