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SC
Q7 Q6 Q5
TO DAC
the 12–bit conversion cycle, the end of the serial output
word, and the validity of the parallel data output.
Externally Controlled 12–Bit ADC (Figure 5)
In this circuit the external pulse starts the first SAR and
simultaneously resets the cascaded second SAR. When Q4
of the first SAR goes high, the second SAR starts conver-
sion, and the first one stops conversion. EOC indicates that
the parallel data are valid and that the serial output is com-
plete. Updating the output data is started with every external
control pulse.
SC
MC14549B MC14559B
6–404
C
S out
MC14559B
Q4 Q3 Q2 Q1 Q0
FF
EOC
Figure 4. Continuously Cycling 12–Bit ADC
C
S out
MC14559B
Q7 Q6 Q5
Q4 Q3 Q2 Q1 Q0
FF
EOC
TO DAC
Figure 5. Externally Controlled 12–Bit ADC
C
S out
SC
MC14549B
MR
Q7 Q6 Q5
Q4 Q3 Q2 Q1 Q0 EOC
TO DAC
EOC
Additional Motorola Parts for Successive
Approximation ADC
Monolithic digital–to–analog converters — The
MC1408/1508 converter has eight–bit resolution and is avail-
able with 6, 7, and 8–bit accuracy. The amplifier–compara-
tor block — The MC1407/1507 contains a high speed
operational amplifier and a high speed comparator with ad-
justable window.
With these two linear parts it is possible to construct SA–
ADCs with an accuracy of up to eight bits, using as the regis-
ter one MC14549B or one MC14559B. An additional CMOS
block will be necessary to generate the clock frequency.
Additional information on successive approximation ADC
is found in Motorola Application Note AN–716.
C
SC
MC14549B
MR
Q7 Q6 Q5
Q4 Q3 Q2 Q1 Q0 EOC
TO DAC
S out
S out
EOC
S out
MOTOROLA CMOS LOGIC DATA
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