Advertisement
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3-Digit BCD Counter
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered
BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock which
drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
TTL Compatible Outputs
On–Chip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
MAXIMUM RATINGS*
(Voltages Referenced to V SS )
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
Symbol
Parameter
V DD
DC Supply Voltage
V in , V out
Input or Output Voltage (DC or Transient)
I in
Input Current (DC or Transient), per Pin
I out
Output Current (DC or Transient), per Pin
P D
Power Dissipation, per Package†
T stg
Storage Temperature
T L
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic "P and D/DW" Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic "L" Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
TRUTH TABLE
Inputs
Master
Reset
Clock
Disable
0
0
0
X
0
1
0
1
0
0
0
X
0
X
1
X
X = Don't Care
MC14553B
6–412
– 0.5 to + 18.0
– 0.5 to V DD + 0.5
– 65 to + 150
LE
Outputs
0
0
No Change
0
0
Advance
1
X
No Change
0
Advance
0
No Change
X
X
No Change
X
Latched
X
1
Latched
X
0
Q0 = Q1 = Q2 = Q3 = 0
Value
Unit
V
V
10
mA
+ 20
mA
500
mW
_ C
_ C
260
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V in and V out should be constrained
to the range V SS
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V SS
or V DD ). Unused outputs must be left open.
MC14553B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBDW
SOIC
T A = – 55 to 125 C for all packages.
BLOCK DIAGRAM
4
3
CIA
CIB
Q0
CLOCK
Q1
12
Q2
LE
10
Q3
O.F.
11
DIS
DS1
DS2
13
MR
DS3
V DD = PIN 16
V SS = PIN 8
v
v
(V in or V out )
V DD .
MOTOROLA CMOS LOGIC DATA
9
7
6
5
14
2
1
15
Advertisement
