Motorola CMOS Logic Manual page 64

V DD
500 µF
I D
V in
PULSE
GENERATOR
7
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
The MC14007UB dual pair plus inverter, which has access
to all its elements offers a number of unique circuit applica-
tions. Figures 1, 5, and 6 are a few examples of the device
flexibility.
DISABLE 3
INPUT 10
DISABLE 6
INPUT DISABLE
1
0
X
X = Don't Care
Figure 5. 3–State Buffer
MC14007UB
6–26
0.01 µF
CERAMIC
14
V out
C L
V SS
APPLICATIONS
+ V DD
2
1
11
12 OUTPUT
9
8
7
OUTPUT
0 0
0 1
1 OPEN
20 ns
90%
V in 50%
10%
t PHL
90%
50%
V out
10%
t THL
V DD
14
13
11
10 12
B
9
5
3
C
4
6
A
Substrates of P–channel devices internally connected to V DD ;
Substrates of N–channel devices internally connected to V SS .
Figure 6. AOI Functions Using Tree Logic
MOTOROLA CMOS LOGIC DATA
20 ns
V DD
V SS
t PLH
V OH
V OL
t TLH
OUT = A+B C
2
1
OUTPUT
8
7