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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 2-Wide, 2-Input
Expandable AND-OR-INVERT
Gate
The MC14506UB is an expandable AND–OR–INVERT gate with inhibit
and 3–state output. The expand option allows cascading with any other gate,
which may be carried as far as desired as long as the propagation delay
added with each gate is considered. For example, the second AOI gate in
this device may be used to expand the first gate, giving an expanded 4–wide,
2–input AOI gate. This device is useful in data control and digital multiplexing
applications.
3–State Output
Separate Inhibit Line
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
MAXIMUM RATINGS*
(Voltages Referenced to V SS )
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
Symbol
Parameter
V DD
DC Supply Voltage
V in , V out
Input or Output Voltage (DC or Transient)
I in , I out
Input or Output Current (DC or Transient),
per Pin
P D
Power Dissipation, per Package†
T stg
Storage Temperature
T L
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic "P and D/DW" Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic "L" Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
A A 1
B A 2
C A 3
D A 4
E A 5
INH 6
3–STATE
DIS 14
OUTPUT DISABLE
E B 13
D B 12
C B 11
B B 10
A B 9
MC14506UB
6–238
Value
– 0.5 to + 18.0
– 0.5 to V DD + 0.5
500
– 65 to + 150
260
LOGIC DIAGRAM
Z = (AB + CD + E + I)
T A = – 55 to 125 C for all packages.
Unit
V
This device contains protection circuitry to
guard against damage due to high static
V
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
10
mA
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
mW
operation, V in and V out should be constrained
_ C
to the range V SS
Unused inputs must always be tied to an
_ C
appropriate logic voltage level (e.g., either V SS
or V DD ). Unused outputs must be left open.
A B C D E
0 0 0 0 1
0 X 0 X 1
0 X X 0 1
X 0 0 X 1
15 Z A
X 0 X 0 1
1 1 X X X
X X 1 1 X
X X X X 0
V DD = PIN 16
X X X X X
V SS = PIN 8
X X X X X
X = Don't Care
7 Z B
MC14506UB
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXUBCP
Plastic
MC14XXXUBCL
Ceramic
MC14XXXUBD
SOIC
v
v
(V in or V out )
V DD .
TRUTH TABLE
Inhibit Disable
0
0
0
0
0
0
0
0
0
0
X
0
X
0
X
0
1
0
X
1
Impedance
MOTOROLA CMOS LOGIC DATA
Z
1
1
1
1
1
0
0
0
0
High
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