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0.01 µF
V DD
16
V in
8
I DD
V in
Figure 1. Power Dissipation Test Circuit
and Waveform
PULSE
GENERATOR
INPUT
(A)
Figure 2. Input "NAND" Gate Switching Time Test Circuit and Waveforms
INPUT (A)
PULSE
GENERATOR
Output (B) = "NOR"
Output (C) = "NOR–Inverter"
Figure 3. "NOR" Gate and "NOR–Inverter" Switching Time Test Circuit and Waveforms
MC14501UB
6–226
CERAMIC
C L
C L
C L
C L
50% DUTY CYCLE
500 µF
20 ns
V DD
90%
90%
10%
10%
V SS
20 ns
V DD
16
OUTPUT
(B)
C L
8
V SS
OUTPUT (B)
OUTPUT (C)
C L
C L
All unused inputs
connected to ground.
PIN ASSIGNMENT
IN 1 A
1
IN 2 A
2
IN 3 A
3
IN 4 A
4
IN 1 C
5
IN 2 C
6
IN 3 C
7
V SS
8
20 ns
20 ns
90%
90%
INPUT (A)
50%
10%
t PHL
t PLH
90%
OUTPUT (B)
50%
10%
t THL
20 ns
90%
50%
INPUT (A)
10%
t PHL
90%
OUTPUT (B)
50%
10%
t THL
t PLH
90%
50%
OUTPUT (C)
10%
t TLH
MOTOROLA CMOS LOGIC DATA
16
V DD
OUT B
15
14
OUT B
13
OUT A
12
IN 2 B
11
IN 1 B
10
OUT C
9
IN 4 C
V DD
50%
10%
V SS
V OH
90%
50%
10%
V OL
t TLH
V DD
V SS
t PLH
V OH
V OL
t TLH
t PHL
V OH
V OL
t THL
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