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B AND UB SERIES FAMILY DATA
The CMOS Devices in this volume which have a B or UB
suffix meet the minimum values for the industry–standard-
ized# family specification. These standardized values are
shown in the Maximum Ratings and Electrical Characteris-
tics Tables. In addition to a standard minimum specification
for characteristics the B/UB devices feature:
3–18 volt operational limits
Capable of driving two low–power TTL loads or one low–
power Schottky TTL load over the rated temperature
range
Direct Interface to High–Speed CMOS
Maximum input current of
over the temperature range
Parameters specified at 5.0, 10, and 15 volt supply
Noise margins: B Series
1.0 V min @ 5.0 V supply
2.0 V min @ 10 V supply
2.5 V min @ 15 V supply
UB Series
0.5 V min @ 5.0 V supply
1.0 V min @ 10 V supply
1.0 V min @ 15 V supply
The industry–standardized maximum ratings are shown at
the bottom of this page. Limits for the static characteristics
are shown in two formats: Table 1 is in the industry format
and Table 2 is in the equivalent Motorola format. The
Motorola format is used throughout this data book. Additional
specification values are shown on the individual data sheets.
Switching characteristics for the B and UB series devices
are specified under the following conditions:
Load Capacitance, C L , of 50 pF
Input Voltage equal to V SS – V DD (Rail–to–Rail swing)
Input pulse rise and fall times of 20 ns
Propagation Delay times measured from 50% point of
input voltage to 50% point of output voltage
Three different supply voltages: 5, 10, and 15 V
Exceptions to the B and UB Series Family
Specification
There are a number of devices which have a B or UB suffix
whose inputs and/or outputs vary somewhat from the family
specification because of functional requirements. Some
categories of notable exceptions are:
Devices with specialized outputs on the chip, such as
NPN emitter–follower drivers or transmission gates, do
not meet output specifications.
#Specifications coordinated by EIA/JEDEC Solid–State Products
Council.
CHAPTER 4
4–2
1 µA at 15 volt power supply
Devices with specialized inputs, such as oscillator in-
puts, have unique input specifications.
Input Voltage
The input voltage specification is interpreted as the worst-
case input voltage to produce an output level of "1" or "0".
This "1" or "0" output level is defined as a deviation from the
supply (V DD ) and ground (V SS ) levels. For a 5.0 V supply,
this deviation is 0.5 V; for a 10 V supply, 1.0 V; and for 15 V,
1.5 V. As an example, in a device operating at a 5.0 V supply,
the device with the input starting at ground is guaranteed to
switch on or before 3.5 V and not to switch up to 1.5 V.
Switching and not switching are defined as within 0.5 V of the
ideal output level for the example with a 5.0 V supply. The
actual switching level referred to the input is between 1.5 V
and 3.5 V.
Noise Margin
The values for input voltages and the defined output devi-
ations lead to the calculated noise margins. Noise margin is
defined as the difference between V IL or V IH and V out
(output deviation). As an example, for a noninverting buffer at
V DD = 5.0 volts: V IL = 1.5 volts and V out = 0.5 volts. There-
fore, Noise Margin equals V IL – V out = 1.0 volt. This figure is
useful while cascading stages (See Figure 1). With the input
to the first stage at a worst–case voltage level (V IL = 1.5 V),
the output is guaranteed to be no greater than 0.5 volts with
a 5.0 volt supply. Since the maximum allowable logic 0 for
the second stage is 1.5 volts, this 0.5 volt output provides a
1.0 volt margin for noise to the next stage.
Output Drive Current
Devices in the B Series are capable of sinking a minimum
of 0.36 mA over the temperature range with a 5.0 V supply.
This value guarantees that these CMOS devices will drive
one low–power Schottky TTL input.
B Series vs UB CMOS
The primary difference between B series and UB series
devices is that UB series gates and inverters are constructed
with a single inverting stage between input and output. The
decreased gain caused by using a single stage results in less
noise immunity and a transfer characteristic that is less ideal.
The decreased gain is quite useful when CMOS Gates and
inverters are used in a "Linear" mode to form oscillators,
monostables, or amplifiers. The decreased gain results in in-
creased stability and a "cleaner" output waveform. In addition
to linear operation, the UB gates and inverters offer an in-
crease in speed, since only a single stage is involved.
The B and UB series, and devices with no suffix can be
used interchangeably in digital circuits that interface to other
CMOS devices, such as High–Speed CMOS Logic.
MOTOROLA CMOS LOGIC DATA
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