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OSC in OR
OSC out
INPUT
A
B
C
D
E
F
AB
AB
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, V in and V out should be constrained to the range V SS
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must
be left open.
MC14490
6–216
IN
OUT
BE 1
A
IN
OUT
BE 2
B
A ACTIVE LOW
B ACTIVE LOW
Figure 9. Single Pulse Output Circuit
Figure 10. Multiple Output Signal Timing Diagram
A
AB
B
(V in or V out )
V DD .
MOTOROLA CMOS LOGIC DATA
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