Motorola CMOS Logic Manual page 246

INPUT DISABLE
STROBE 2
STROBE 1
MINIMUM COINCIDENCE =
50%
SET A
OUTPUT SET
50%
OUTPUT INHIBIT
CLOCK
OUTPUT A
t PLH
Mode 1: OUTPUT SET Initiates Time Delay
INPUT DISABLE
STROBE 2
STROBE 1
50%
SET A
OUTPUT SET
OUTPUT INHIBIT
CLOCK
OUTPUT A 50%
t PLH
Mode 3: OUTPUT INHIBIT Disables Time Delay
Figure 2. Typical Operation Modes and Functional Timing Diagram
MC14415
6–208
500 ns @ V DD = 4.75 Vdc
1 2 100
50%
t PHL
50%
1 2 100
t PHL t PLH t PHL
INPUT DISABLE
STROBE 2
STROBE 1
MINIMUM COINCIDENCE =
50%
SET A
OUTPUT SET
OUTPUT INHIBIT
CLOCK 1
OUTPUT A 50%
t PLH
Mode 2: Set A Initiates Time Delay
INPUT DISABLE
50%
STROBE 2
STROBE 1
SET A
OUTPUT SET
CLOCK
OUTPUT A
t PLH
Mode 4: Positive–Edge Strobe (ST2)
Initiates Time Delay
MOTOROLA CMOS LOGIC DATA
500 ns @ V DD = 4.75 Vdc
2 100
t PHL
MINIMUM COINCIDENCE =
500 ns @ V DD = 4.75 Vdc
1 100
50%
t PHL