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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
BCD Up/Down Counter
The MC14510B synchronous up/down BCD counter is constructed with
MOS P–channel and N–channel enhancement mode devices in a monolithic
structure. The counter consists of type D flip–flop stages with a gating
structure to provide type T flip–flop capability.
This counter can be preset by applying the desired value in BCD to the
Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the
Reset (R) pin.
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to–
digital and digital–to–analog conversions, and (3) Magnitude and sign
generation.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock
Asynchronous Preset Enable Operation
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
MAXIMUM RATINGS*
(Voltages Referenced to V SS )
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
Symbol
Parameter
V DD
DC Supply Voltage
V in , V out
Input or Output Voltage (DC or Transient)
I in , I out
Input or Output Current (DC or Transient),
per Pin
P D
Power Dissipation, per Package†
T stg
Storage Temperature
T L
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the may occur.
†Temperature Derating:
Plastic "P and D/DW" Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic "L" Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
Preset
Enable
Carry In
Up/Down
1
X
0
1
0
0
X
X
X
X
X = Don't Care
NOTE: When counting up, the Carry Out signal is normally high, and is low only
when Q1 and Q4 are high and Carry In is low. When counting down, Carry
Out is low only when Q1 through Q4 and Carry In are low.
MC14510B
6–248
– 0.5 to + 18.0
– 0.5 to V DD + 0.5
– 65 to + 150
TRUTH TABLE
Reset
Clock
0
0
X
0
0
0
0
1
0
X
X
1
X
Value
Unit
V
V
10
mA
500
mW
_ C
_ C
260
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
Action
operation, V in and V out should be constrained
No Count
to the range V SS
Count Up
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V SS
Count Down
or V DD ). Unused outputs must be left open.
Preset
Reset
MC14510B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBD
SOIC
T A = – 55 to 125 C for all packages.
BLOCK DIAGRAM
1
PE
Q1
6
5
CARRY IN
9
R
Q2
11
10
UP/DOWN
15
CLOCK
Q3
14
4
P1
12
P2
Q4
2
13
P3
CARRY
3
P4
7
OUT
V DD = PIN 16
V SS = PIN 8
v
v
(V in or V out )
V DD .
MOTOROLA CMOS LOGIC DATA
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