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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Gate
The MC14572UB hex functional gate is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic structure.
These complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired. The chip contains four
inverters, one NOR gate and one NAND gate.
Diode Protection on All Inputs
Single Supply Operation
Supply Voltage Range = 3.0 Vdc to 18 Vdc
NOR Input Pin Adjacent to V SS Pin to Simplify Use As An Inverter
NAND Input Pin Adjacent to V DD Pin to Simplify Use As An Inverter
NOR Output Pin Adjacent to Inverter Input Pin For OR Application
NAND Output Pin Adjacent to Inverter Input Pin For AND Application
Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
MAXIMUM RATINGS*
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
(Voltages Referenced to V SS )
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
Symbol
Parameter
V DD
DC Supply Voltage
V in , V out
Input or Output Voltage (DC or Transient)
I in , I out
Input or Output Current (DC or Transient),
per Pin
P D
Power Dissipation, per Package†
T stg
Storage Temperature
T L
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic "P and D/DW" Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic "L" Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
V DD
7
2
1
6
V SS
MOTOROLA CMOS LOGIC DATA
– 0.5 to + 18.0
– 0.5 to V DD + 0.5
– 65 to + 150
CIRCUIT SCHEMATIC
V DD
14
5
15
V SS
Value
Unit
V
V
10
mA
500
mW
_ C
_ C
260
V DD
13
V SS
MC14572UB
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXUBCP
Plastic
MC14XXXUBCL
Ceramic
MC14XXXUBD
SOIC
T A = – 55 to 125 C for all packages.
LOGIC DIAGRAM
2
1
4
3
6
5
7
10
9
12
11
14
13
15
V DD = PIN 16
V SS = PIN 8
MC14572UB
6–481
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