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A 12
B 13
R tc 1
8–STAGE
C tc 2
OSC
C
COUNTER
R S 3
RESET
AUTO RESET
POWER–ON
5
RESET
V DD = PIN 14
V SS = PIN 7
FREQUENCY SELECTION TABLE
Number of
Counter Stages
A
B
0
0
0
1
1
0
1
1
3
MC14541B
6–380
EXPANDED BLOCK DIAGRAM
2 10 2 13 2 16
2 8
C 8–STAGE
COUNTER
RESET
6
MASTER RESET
Count
2 n
n
13
8192
10
1024
8
256
16
65536
INTERNAL
RESET
R S
Figure 3. Oscillator Circuit Using RC Configuration
1 OF 4
MUX
RESET
10
MODE
TRUTH TABLE
Pin
Auto Reset,
5
Auto Reset Operating
Master Reset, 6
Timer Operational
Q / Q,
9
Output Initially Low
After Reset
Mode,
10
Single Cycle Mode
TO CLOCK
CIRCUIT
2
1
C tc
R TC
8 Q
9
Q/Q
SELECT
State
0
1
Auto Reset Disabled
Master Reset On
Output Initially High
After Reset
Recycle Mode
MOTOROLA CMOS LOGIC DATA
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