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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
UB-Suffix Series CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
non–buffered functions.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linear and Oscillator Applications
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
Devices
LOGIC DIAGRAMS
MC14001UB
Quad 2–Input
NOR Gate
1
3
2
5
4
6
8
10
10
9
12
11
11
13
12
MC14012UB
Dual 4–Input
NAND Gate
2
3
1
4
5
9
10
13
11
11
12
12
13
NC = 6, 8
MC14001UB
6–14
MC14002UB
MC14011UB
Dual 4–Input
Quad 2–Input
NOR Gate
NAND Gate
2
1
3
2
1
4
5
6
5
9
8
9
13
12
13
NC = 6, 8
MC14023UB
MC14025UB
Triple 3–Input
Triple 3–Input
NAND Gate
NOR Gate
1
1
2
2
9
8
8
3
3
4
6
4
5
5
11
10
12
13
V DD = PIN 14
V SS = PIN 7
FOR ALL DEVICES
MC14001UB
Quad 2-Input NOR Gate
MC14002UB
Dual 4-Input NOR Gate
MC14011UB
Quad 2-Input NAND Gate
MC14012UB
Dual 4-Input NAND Gate
MC14023UB
Triple 3-Input NAND Gate
MC14025UB
Triple 3-Input NOR Gate
3
4
10
11
ORDERING INFORMATION
9
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
6
T A = – 55 to 125 C for all packages.
10
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V in and V out should be constrained
v
to the range V SS
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V SS
or V DD ). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATA
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
Plastic
Ceramic
SOIC
v
(V in or V out )
V DD .
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