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Motorola HC12 Refrence Manual

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  Summary of Contents for Motorola HC12

  • Page 1 Order this document by CPU12RM/AD Rev. 1.0 HC12 HC12 HC12 CPU12 Reference Manual...
  • Page 2 Motorola products are not designed, intended, or authorized for use as components in systems...
  • Page 3: Table Of Contents

    Addition and Subtraction Instructions............... 5-3 Binary Coded Decimal Instructions ..............5-4 Decrement and Increment Instructions ............5-4 Compare and Test Instructions ................ 5-5 Boolean Logic Instructions ................5-6 5.10 Clear, Complement, and Negate Instructions ..........5-6 CPU12 MOTOROLA REFERENCE MANUAL...
  • Page 4 Software Interrupt Instruction ................7-6 Exception Processing Flow ................7-6 SECTION 8 DEVELOPMENT AND DEBUG SUPPORT External Reconstruction of the Queue ............. 8-1 Instruction Queue Status Signals..............8-1 Implementing Queue Reconstruction............... 8-3 Background Debug Mode ................8-6 Instruction Tagging..................8-13 MOTOROLA CPU12 REFERENCE MANUAL...
  • Page 5 CPU12 Design Goals ..................B-1 Source Code Compatibility................B-1 Programmer’s Model and Stacking ..............B-3 True 16-Bit Architecture ...................B-3 Improved Indexing....................B-6 Improved Performance..................B-9 Additional Functions..................B-11 APPENDIX C HIGH-LEVEL LANGUAGE SUPPORT Data Types...................... C-1 Parameters and Variables................C-1 Increment and Decrement Operators.............. C-3 CPU12 MOTOROLA REFERENCE MANUAL...
  • Page 6 Page Higher Math Functions ..................C-3 Conditional If Constructs ................. C-4 Case and Switch Statements ................C-4 Pointers ......................C-4 Function Calls ....................C-4 Instruction Set Orthogonality................C-5 APPENDIX D ASSEMBLY LISTING INDEX SUMMARY OF CHANGES MOTOROLA CPU12 REFERENCE MANUAL...
  • Page 7 Abnormal Membership Function Case 2............9-13 Abnormal Membership Function Case 3............9-13 REV Instruction Flow Diagram ............... 9-16 9-10 REVW Instruction Flow Diagram..............9-21 9-11 WAV and wavr Instruction Flow Diagram............9-25 9-12 Endpoint Table Handling................9-28 CPU12 MOTOROLA REFERENCE MANUAL...
  • Page 8 MOTOROLA CPU12 viii REFERENCE MANUAL...
  • Page 9 BDM Firmware Commands................8-11 BDM Register Mapping .................. 8-11 Tag Pin Function .................... 8-13 10-1 Mapping Precedence ..................10-2 Instruction Set Summary..................A-2 CPU12 Opcode Map ..................A-20 Indexed Addressing Mode Summary .............A-22 Indexed Addressing Mode Postbyte Encoding (xb) ........A-23 CPU12 MOTOROLA REFERENCE MANUAL...
  • Page 10 LIST OF TABLES Transfer and Exchange Postbyte Encoding...........A-24 Loop Primitive Postbyte Encoding (lb) ............A-25 Translated M68HC11 Mnemonics..............B-2 Instructions with Smaller Object Code .............B-3 Comparison of Math Instruction Speeds ............B-10 New M68HC12 Instructions ................B-11 MOTOROLA CPU12 REFERENCE MANUAL...
  • Page 11: Introduction

    An instruction queue buffers program information so the CPU has immediate access to at least three bytes of machine code at the start of every instruction. In addition to the addressing modes found in other Motorola MCUs, the CPU12 offers an extensive set of indexed addressing capabilities including: •...
  • Page 12: Symbols And Notation

    PPAGE — Program overlay page (bank) number for extended memory (>64K). Page — Program overlay page — High-order byte — Low-order byte ( ) — Content of register or memory location $ — Hexadecimal value % — Binary value MOTOROLA INTRODUCTION CPU12 REFERENCE MANUAL...
  • Page 13 A specific mnemonic within a range is referred to by mnemonic and number. A7 is bit 7 of accumulator A. A range of mnemonics is referred to by mnemonic and the numbers that define the range. DATA[15:8] form the high byte of the data bus. CPU12 INTRODUCTION MOTOROLA REFERENCE MANUAL...
  • Page 14 MOTOROLA INTRODUCTION CPU12 REFERENCE MANUAL...
  • Page 15: Overview

    PROGRAM COUNTER S X H I Z V C CONDITION CODE REGISTER HC12 PROG MODEL Figure 2-1 Programming Model 2.1.1 Accumulators General-purpose 8-bit accumulators A and B are used to hold operands and results of operations. Some instructions treat the combination of these two 8-bit accumulators (A : B) as a 16-bit double accumulator (D).
  • Page 16 M68HC11. 2.1.4 Program Counter The program counter (PC) is a 16-bit register that holds the address of the next instruc- tion to be executed. It is automatically incremented each time an instruction is fetched. MOTOROLA OVERVIEW CPU12 REFERENCE MANUAL...
  • Page 17 I bit are automatically set to prevent other interrupts from being recognized during the interrupt service routine. The mask bits are set after the registers are stacked, but before the interrupt vector is fetched. CPU12 OVERVIEW MOTOROLA REFERENCE MANUAL...
  • Page 18 The INX, DEX, INY, and DEY instructions affect the Z bit and no other condition flags. These operations can only determine = and ≠. 2.1.5.7 V Status Bit The V bit is set when two’s complement overflow occurs as a result of an operation. MOTOROLA OVERVIEW CPU12 REFERENCE MANUAL...
  • Page 19: Data Types

    CPU executes more than one instruction at the same time, while the CPU12 always finishes execut- ing an instruction before beginning to execute another. Refer to SECTION 4 IN- STRUCTION QUEUE for more information. CPU12 OVERVIEW MOTOROLA REFERENCE MANUAL...
  • Page 20 MOTOROLA OVERVIEW CPU12 REFERENCE MANUAL...
  • Page 21: Mode Summary

    16-bit constant offset from x, y, sp, or pc (16-bit offset) (16-bit offset in two extension bytes) Indexed-Indirect Pointer to operand is found at... (D accumulator INST [D, xysp ] [D,IDX] x, y, sp, or pc plus the value in D offset) CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
  • Page 22: Effective Address

    16-bit immediate value but only an 8-bit value is supplied. In this case the assembler will generate the 16-bit value $0067 because the CPU ex- pects a 16-bit value in the instruction stream. BRSET FOO,#$03,THERE MOTOROLA ADDRESSING MODES CPU12 REFERENCE MANUAL...
  • Page 23: Direct Addressing Mode

    This addressing mode can be used to access any lo- cation in the 64-Kbyte memory map. Example: LDAA $F03B This is a very basic example of extended addressing. The value from address $F03B is loaded into the A accumulator. CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
  • Page 24: Relative Addressing Mode

    $FC with a BRCLR that accesses memory using an 8-bit indexed postbyte sets up a loop that executes until all the bits in the specified memory byte that corre- spond to ones in the mask byte are cleared. MOTOROLA ADDRESSING MODES CPU12...
  • Page 25: Indexed Addressing Modes

    A special group of instructions (LEAS, LEAX, and LEAY) cause this calculated effective address to be loaded into an index register for further calculations. CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
  • Page 26 In the first example, A will be loaded with the value from address $1000. In the second example, the value from the B accumulator will be stored at address $1FF8 ($2000 – $8). MOTOROLA ADDRESSING MODES CPU12 REFERENCE MANUAL...
  • Page 27 The square brackets distinguish this addressing mode from 16-bit constant offset indexing. Example: LDAA [10,X] CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
  • Page 28 M68HC11 stack, PSHA is equivalent to STAA 1,SP– and PULA is equivalent to LDAA 1,+SP. However, in the M68HC11, 16-bit operations like PSHX and PULX require mul- tiple instructions to decrement the SP by one, then store X, then decrement SP by one again. MOTOROLA ADDRESSING MODES CPU12 REFERENCE MANUAL...
  • Page 29 The square brackets distinguish this ad- dressing mode from D accumulator offset indexing. Example: [D,PC] DC.W PLACE1 DC.W PLACE2 DC.W PLACE3 CPU12 ADDRESSING MODES MOTOROLA REFERENCE MANUAL...
  • Page 30: Instructions Using Multiple Modes

    PC-relative indexing with move instructions by providing for PC offsets in source code. Table 3-3 shows PC offsets from the location immediately following the current in- struction by addressing mode. MOTOROLA ADDRESSING MODES CPU12 3-10 REFERENCE MANUAL...
  • Page 31 $18 is the page pre-byte, 09 is the MOVB opcode for ext-idx, C2 is the indexed post- byte for 2,PC (without correction). The Motorola MCUasm assembler produces corrected object code for PC-relative moves (18 09 C0 20 00 for the example shown). Note that, instead of assembling the 2,PC as C2, the correction has been applied to make it C0.
  • Page 32: Addressing More Than 64 Kbytes

    The RTC instruction restores the saved program page value and the return address from the stack. This causes execution to resume at the next instruction after the orig- inal CALL instruction. Refer to SECTION 10 MEMORY EXPANSION for a detailed discussion of memory ex- pansion. MOTOROLA ADDRESSING MODES CPU12 3-12 REFERENCE MANUAL...
  • Page 33: Instruction Queue

    Two external pins, IPIPE[1:0], provide time-multiplexed information about data move- ment in the queue and instruction execution. Decoding and use of these signals is dis- cussed in SECTION 8 DEVELOPMENT AND DEBUG SUPPORT. CPU12 INSTRUCTION QUEUE MOTOROLA REFERENCE MANUAL...
  • Page 34: Data Movement In The Queue

    The following information is provided to enhance subsequent descriptions of instruction execution. MOTOROLA INSTRUCTION QUEUE CPU12 REFERENCE MANUAL...
  • Page 35 CALL and RTC execute correctly in the normal 64-Kbyte address space, thus provid- ing for portable code. However, since extra execution cycles are required, routinely substituting CALL/RTC for JSR/RTS is not recommended. CPU12 INSTRUCTION QUEUE MOTOROLA REFERENCE MANUAL...
  • Page 36 In all other cases, the op- tional cycle appears as a free cycle. MOTOROLA INSTRUCTION QUEUE CPU12...
  • Page 37 If the queue is not yet ready to advance, the third word of program information is held in the buffer. CPU12 INSTRUCTION QUEUE MOTOROLA REFERENCE MANUAL...
  • Page 38 MOTOROLA INSTRUCTION QUEUE CPU12 REFERENCE MANUAL...
  • Page 39: Instruction Set Overview

    Store instructions automatically update the N and Z condition code bits, which can eliminate the need for a separate test in- struction in some programs. Table 5-1 is a summary of load and store instructions. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
  • Page 40: Transfer And Exchange Instructions

    All the bits in the upper byte of the 16-bit result are given the value of the MSB of the 8-bit number. SECTION 6 INSTRUCTION GLOSSARY contains information concerning other transfers and exchanges between 8- and 16-bit registers. Table 5-2 is a summary of transfer and exchange instructions. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 REFERENCE MANUAL...
  • Page 41: Move Instructions

    Signed and unsigned 8- and 16-bit subtraction can be performed between registers or between registers and memory. Special instructions support index calculation. Instruc- tions that subtract the CCR carry bit facilitate multiple precision computation. Refer to Table 5-4 for addition and subtraction instructions. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
  • Page 42: Binary Coded Decimal Instructions

    CCR, they are particularly well suited for loop counters in multiple-precision computation routines. Refer to 5.19 Loop Primitive Instructions for information con- cerning automatic counter branches. Table 5-6 is a summary of decrement and incre- ment instructions. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 REFERENCE MANUAL...
  • Page 43: Compare And Test Instructions

    Test Instructions Mnemonic Function Operation Test Memory for Zero or Minus (M) – $00 TSTA Test A for Zero or Minus (A) – $00 TSTB Test B for Zero or Minus (B) – $00 CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
  • Page 44: Boolean Logic Instructions

    Two’s Complement Memory $00 – (A) ⇒ A or (A) + 1 ⇒ A NEGA Two’s Complement A $00 – (B) ⇒ B or (B) + 1 ⇒ B NEGB Two’s Complement B MOTOROLA INSTRUCTION SET OVERVIEW CPU12 REFERENCE MANUAL...
  • Page 45: Multiplication And Division Instructions

    (M) • (mm) ⇒ M BCLR Clear Bits in Memory (A) • (M) BITA Bit Test A (B) • (M) BITB Bit Test B (M) + (mm) ⇒ M BSET Set Bits in Memory CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
  • Page 46: Shift And Rotate Instructions

    Rotate Left Memory Through Carry ROLA Rotate Left A Through Carry ROLB Rotate Left B Through Carry Rotate Right Memory Through Carry RORA Rotate Right A Through Carry RORB Rotate Right B Through Carry MOTOROLA INSTRUCTION SET OVERVIEW CPU12 REFERENCE MANUAL...
  • Page 47: Fuzzy Logic Instructions

    Because WAV requires a number of cycles to execute, it can be interrupted. The wavr pseudo-instruction causes execution to resume at the point it was interrupted. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL...
  • Page 48 Weighted Average Calculation Results Are Placed in Correct Registers ∑ ⇒ For EDIV immediately After WAV Resumes Execution of Recover immediate results from stack wavr Interrupted WAV Instruction rather than initializing them to zero. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-10 REFERENCE MANUAL...
  • Page 49: Maximum And Minimum Instructions

    8- to 16-bit multiply and accumulate operation that obtains a numerator for the weighted average calculation. The EMACS instruction can auto- mate this portion of the averaging operation when 16-bit operands are used. Table 5- shows the EMACS instruction. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-11...
  • Page 50: Table Interpolation Instructions

    8-Bit Table Lookup and Interpolate Initialize B, and index before TBL. (no indirect addressing modes allowed.) <ea> points to the first 8-bit table entry (M) B is fractional part of lookup value. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-12 REFERENCE MANUAL...
  • Page 51: Branch Instructions

    This permits branching from any location in the standard 64-Kbyte address map to any other loca- tion in the map. Table 5-18 is a summary of the long branch instructions. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-13...
  • Page 52 Branch if Greater Than R ≤ M Z + (N ⊕ V) = 1 Branch if Less Than or Equal R < M N ⊕ V = 1 Branch if Less Than MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-14 REFERENCE MANUAL...
  • Page 53 Long Branch if Greater Than V) = 0 ⊕ Z + (N LBLE Long Branch if Less Than or Equal V) = 1 ⊕ LBLT Long Branch if Less Than V = 1 CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-15...
  • Page 54: Loop Primitive Instructions

    Test counter and branch if ≠ 0 If (counter) not = 0, then branch TBNE (counter = A, B, D, X,Y, or SP) else continue to next instruction MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-16 REFERENCE MANUAL...
  • Page 55: Jump And Subroutine Instructions

    Subroutine address ⇒ : PC (SP) (SP+1) Return from Call ⇒ SP + 2 ⇒ PPAGE (SP) ⇒ SP + 1 Return from Subroutine ⇒ : PC (SP) (SP+1) ⇒ SP + 2 CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-17...
  • Page 56: Interrupt Instructions

    (SP+1) ⇒ ⇒ TRAP Software Interrupt SP – 2 SP; X (SP) (SP+1) ⇒ ⇒ SP; B : A SP – 2 (SP) (SP+1) ⇒ ⇒ SP – 1 SP; CCR (SP) MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-18 REFERENCE MANUAL...
  • Page 57: Index Manipulation Instructions

    (A, B, CCR, D, X, Y, or SP) ⇔ (A, B, CCR, D, X, Y, or SP) Exchange Register to Register (D) ⇔ (X) XGDX EXchange D with X (D) ⇔ (Y) XGDY EXchange D with Y CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-19...
  • Page 58: Stacking Instructions

    8-bit accumulators A and B or 16-bit accumulator D to be added to the contents of the X and Y index registers, the SP, or the PC. Table 5-25 is a summary of pointer and index instructions. MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-20 REFERENCE MANUAL...
  • Page 59: Condition Code Instructions

    The wait instruction (WAI) stacks a return address and the contents of CPU registers and accumulators, then waits for an interrupt service request; however, system clock signals continue to run. CPU12 INSTRUCTION SET OVERVIEW MOTOROLA REFERENCE MANUAL 5-21...
  • Page 60: Background Mode And Null Operations

    Mnemonic Function Operation If BDM enabled, enter BDM; BGND Enter Background Debug Mode else, resume normal processing Branch Never Does not branch LBRN Long Branch Never Does not branch Null operation — MOTOROLA INSTRUCTION SET OVERVIEW CPU12 5-22 REFERENCE MANUAL...
  • Page 61: Instruction Glossary

    Address Mode Obje #opr16i CE jj opr8a DE d opr16a FE h oprx0_xysp ID X DETAILED SYNTAX oprx9,xysp IDX1 oprx16,xysp IDX2 CYCLE-BY-CYCLE [D,xysp] [D,IDX] OPERATION [oprx16,xysp] [IDX2] EX GLO PG Figure 6-1 Example Glossary Page CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL...
  • Page 62: Condition Code Changes

    — Signed relative offset $80 (–128) to $7F (+127). Offset relative to the byte following the relative offset byte, or low-order byte of a 16-bit relative offset for long branches. xb — Indexed addressing post-byte. MOTOROLA INSTRUCTION GLOSSARY CPU12 REFERENCE MANUAL...
  • Page 63: Source Forms

    D, index registers X or Y, or the SP. Some assemblers may accept t2, T2, t3, or T3 codes in certain cases of transfer and exchange instructions, but these forms are intended for Motorola use only. abd — Any one legal register designator for accumulators A or B or the double accumu- lator D.
  • Page 64 — Any one legal register designation for index registers X or Y, the SP, or the PC. The reference point for PC relative instructions is the next address after the last byte of object code for the current instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12...
  • Page 65: Cycle-By-Cycle Execution

    — Write 8-bit PPAGE register. These cycles are only used with the CALL and RTC instructions to write the destination value of the PPAGE register and are not vis- ible on the external bus. Since the PPAGE register is an internal 8-bit register, these cycles are never stretched. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL...
  • Page 66 — Unstack 8-bit data. These cycles are stretched only when controlled by a chip- select circuit programmed for slow memory. MOTOROLA INSTRUCTION GLOSSARY CPU12 REFERENCE MANUAL...
  • Page 67 The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetch- es from that address. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL...
  • Page 68: Glossary

    A7 • B7 + B7 • R7 + R7 • A7 Set if there was a carry from the MSB of the result; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 06 MOTOROLA INSTRUCTION GLOSSARY CPU12 REFERENCE MANUAL...
  • Page 69 Address Mode Object Code Cycles Access Detail ABX translates to... 1A E5 LEAX B,X Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL...
  • Page 70 Object Code Cycles Access Detail ABY translates to... 19 ED LEAY B,Y Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-10 REFERENCE MANUAL...
  • Page 71 A9 xb ADCA oprx9,xysp IDX1 A9 xb ff ADCA oprx16,xysp IDX2 A9 xb ee ff frPP ADCA [D ,xysp ] [D,IDX] A9 xb fIfrfP ADCA [ oprx16,xysp ] [IDX2] A9 xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-11...
  • Page 72 E9 xb ADCB oprx9,xysp IDX1 E9 xb ff ADCB oprx16,xysp IDX2 E9 xb ee ff frPP ADCB [D ,xysp ] [D,IDX] E9 xb fIfrfP ADCB [ oprx16,xysp ] [IDX2] E9 xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-12 REFERENCE MANUAL...
  • Page 73 AB xb ADDA oprx9,xysp IDX1 AB xb ff ADDA oprx16,xysp IDX2 AB xb ee ff frPP ADDA [D ,xysp ] [D,IDX] AB xb fIfrfP ADDA [ oprx16,xysp ] [IDX2] AB xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-13...
  • Page 74 EB xb ADDB oprx9,xysp IDX1 EB xb ff ADDB oprx16,xysp IDX2 EB xb ee ff frPP ADDB [D ,xysp ] [D,IDX] EB xb fIfrfP ADDB [ oprx16,xysp ] [IDX2] EB xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-14 REFERENCE MANUAL...
  • Page 75 E3 xb ADDD oprx9,xysp IDX1 E3 xb ff ADDD oprx16,xysp IDX2 E3 xb ee ff fRPP ADDD [D ,xysp ] [D,IDX] E3 xb fIfRfP ADDD [ oprx16,xysp ] [IDX2] E3 xb ee ff fIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-15...
  • Page 76 A4 xb ANDA oprx9,xysp IDX1 A4 xb ff ANDA oprx16,xysp IDX2 A4 xb ee ff frPP ANDA [D ,xysp ] [D,IDX] A4 xb fIfrfP ANDA [ oprx16,xysp ] [IDX2] A4 xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-16 REFERENCE MANUAL...
  • Page 77 E4 xb ANDB oprx9,xysp IDX1 E4 xb ff ANDB oprx16,xysp IDX2 E4 xb ee ff frPP ANDB [D ,xysp ] [D,IDX] E4 xb fIfrfP ANDB [ oprx16,xysp ] [IDX2] E4 xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-17...
  • Page 78 Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ANDCC # opr8i 10 ii MOTOROLA INSTRUCTION GLOSSARY CPU12 6-18 REFERENCE MANUAL...
  • Page 79 ASL oprx9,xysp IDX1 68 xb ff rPOw ASL oprx16,xysp IDX2 68 xb ee ff frPPw ASL [D ,xysp ] [D,IDX] 68 xb fIfrPw ASL [ oprx16,xysp ] [IDX2] 68 xb ee ff fIPrPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-19...
  • Page 80 (for values of N and C after the shift). Set if the MSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASLA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-20 REFERENCE MANUAL...
  • Page 81 (for values of N and C after the shift). Set if the MSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASLB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-21...
  • Page 82 (for values of N and C after the shift). Set if the MSB of D was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASLD MOTOROLA INSTRUCTION GLOSSARY CPU12 6-22 REFERENCE MANUAL...
  • Page 83 ASR oprx9,xysp IDX1 67 xb ff rPOw ASR oprx16,xysp IDX2 67 xb ee ff frPPw ASR [D ,xysp ] [D,IDX] 67 xb fIfrPw ASR [ oprx16,xysp ] [IDX2] 67 xb ee ff fIPrPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-23...
  • Page 84 (for values of N and C after the shift). Set if the LSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASRA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-24 REFERENCE MANUAL...
  • Page 85 (for values of N and C after the shift). Set if the LSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ASRB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-25...
  • Page 86 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-26 REFERENCE MANUAL...
  • Page 87 BCLR oprx9,xysp, msk8 IDX1 0D xb ff mm rPwP BCLR oprx16,xysp, msk8 IDX2 0D xb ee ff mm frPwOP Notes: 1. Indirect forms of indexed addressing cannot be used with this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-27...
  • Page 88 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-28 REFERENCE MANUAL...
  • Page 89 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-29...
  • Page 90 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-30 REFERENCE MANUAL...
  • Page 91 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail BGND VfPPP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-31...
  • Page 92 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-32 REFERENCE MANUAL...
  • Page 93 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-33...
  • Page 94 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-34 REFERENCE MANUAL...
  • Page 95 A5 xb BITA oprx9,xysp IDX1 A5 xb ff BITA oprx16,xysp IDX2 A5 xb ee ff frPP BITA [D ,xysp ] [D,IDX] A5 xb fIfrfP BITA [ oprx16,xysp ] [IDX2] A5 xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-35...
  • Page 96 E5 xb BITB oprx9,xysp IDX1 E5 xb ff BITB oprx16,xysp IDX2 E5 xb ee ff frPP BITB [D ,xysp ] [D,IDX] E5 xb fIfrfP BITB [ oprx16,xysp ] [IDX2] E5 xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-36 REFERENCE MANUAL...
  • Page 97 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-37...
  • Page 98 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-38 REFERENCE MANUAL...
  • Page 99 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-39...
  • Page 100 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-40 REFERENCE MANUAL...
  • Page 101 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-41...
  • Page 102 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-42 REFERENCE MANUAL...
  • Page 103 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-43...
  • Page 104 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail BRA rel8 20 rr MOTOROLA INSTRUCTION GLOSSARY CPU12 6-44 REFERENCE MANUAL...
  • Page 105 0F xb ff mm rr BRCLR oprx9,xysp, msk8, rel8 IDX1 rffPPP 0F xb ee ff mm BRCLR oprx16,xysp, msk8, rel8 IDX2 frPffPPP Notes: 1. Indirect forms of indexed addressing cannot be used with this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-45...
  • Page 106 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail BRN rel8 21 rr MOTOROLA INSTRUCTION GLOSSARY CPU12 6-46 REFERENCE MANUAL...
  • Page 107 0E xb ff mm rr BRSET oprx9,xysp, msk8, rel8 IDX1 rffPPP 0E xb ee ff mm BRSET oprx16,xysp, msk8, rel8 IDX2 frPffPPP Notes: 1. Indirect forms of indexed addressing cannot be used with this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-47...
  • Page 108 BSET oprx9,xysp, msk8 IDX1 0C xb ff mm rPwP BSET oprx16,xysp, msk8 IDX2 0C xb ee ff mm frPwOP Notes: 1. Indirect forms of indexed addressing cannot be used with this instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-48 REFERENCE MANUAL...
  • Page 109 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail BSR rel8 07 rr PPPS CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-49...
  • Page 110 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-50 REFERENCE MANUAL...
  • Page 111 C = 1 r≥m BHS/BCC Unsigned Carry C = 1 No Carry Simple Negative N = 1 Plus Simple Overflow V = 1 No Overflow Simple Z = 1 r≠0 Simple Always — Never Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-51...
  • Page 112 4B xb ff pg gnfSsPPP CALL oprx16,xysp, page IDX2 4B xb ee ff pg fgnfSsPPP CALL [D ,xysp ] [D,IDX] 4B xb fIignSsPPP CALL [ oprx16,xysp ] [IDX2] 4B xb ee ff fIignSsPPP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-52 REFERENCE MANUAL...
  • Page 113 A7 • B7 + B7 • R7 + R7 + A7 Set if there was a borrow from the MSB of the result; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 17 CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-53...
  • Page 114 Condition Codes and Boolean Formulas: – – – – – – – 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail CLC translates to... 10 FE ANDCC #$FE MOTOROLA INSTRUCTION GLOSSARY CPU12 6-54 REFERENCE MANUAL...
  • Page 115 Condition Codes and Boolean Formulas: – – – – – – – 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail CLI translates to... 10 EF ANDCC #$EF CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-55...
  • Page 116 69 xb CLR oprx9,xysp IDX1 69 xb ff CLR oprx16,xysp IDX2 69 xb ee ff CLR [D ,xysp ] [D,IDX] 69 xb PIfPw CLR [ oprx16,xysp ] [IDX2] 69 xb ee ff PIPPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-56 REFERENCE MANUAL...
  • Page 117 Condition Codes and Boolean Formulas: – – – – 0; Cleared. 1; Set. 0; Cleared. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail CLRA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-57...
  • Page 118 Condition Codes and Boolean Formulas: – – – – 0; Cleared. 1; Set. 0; Cleared. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail CLRB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-58 REFERENCE MANUAL...
  • Page 119 Condition Codes and Boolean Formulas: – – – – – – – 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail CLV translates to... 10 FD ANDCC #$FD CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-59...
  • Page 120 CMPA oprx9,xysp IDX1 A1 xb ff CMPA oprx16,xysp IDX2 A1 xb ee ff frPP CMPA [D, xysp ] [D,IDX] A1 xb fIfrfP CMPA [ oprx16 , xysp ] [IDX2] A1 xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-60 REFERENCE MANUAL...
  • Page 121 E1 xb ff CMPB oprx16 , xysp IDX2 E1 xb ee ff frPP CMPB [D, xysp ] [D,IDX] E1 xb fIfrfP CMPB [ oprx16 , xysp ] [IDX2] E1 xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-61...
  • Page 122 IDX1 61 xb ff rPOw COM oprx16 xysp IDX2 61 xb ee ff frPPw xysp ] COM [D [D,IDX] 61 xb fIfrPw COM [ oprx16 xysp ] [IDX2] 61 xb ee ff fIPrPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-62 REFERENCE MANUAL...
  • Page 123 Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. 1; Set (for M6800 compatibility). Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail COMA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-63...
  • Page 124 Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. 1; Set (for M6800 compatibility). Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail COMB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-64 REFERENCE MANUAL...
  • Page 125 AC xb CPD oprx9,xysp IDX1 AC xb ff CPD oprx16,xysp IDX2 AC xb ee ff fRPP CPD [D ,xysp ] [D,IDX] AC xb fIfRfP CPD [ oprx16,xysp ] [IDX2] AC xb ee ff fIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-65...
  • Page 126 AF xb CPS oprx9,xysp IDX1 AF xb ff CPS oprx16,xysp IDX2 AF xb ee ff fRPP CPS [D ,xysp ] [D,IDX] AF xb fIfRfP CPS [ oprx16,xysp ] [IDX2] AF xb ee ff fIPRfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-66 REFERENCE MANUAL...
  • Page 127 AE xb CPX oprx9,xysp IDX1 AE xb ff CPX oprx16,xysp IDX2 AE xb ee ff fRPP CPX [D ,xysp ] [D,IDX] AE xb fIfRfP CPX [ oprx16,xysp ] [IDX2] AE xb ee ff fIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-67...
  • Page 128 AD xb CPY oprx9,xysp IDX1 AD xb ff CPY oprx16,xysp IDX2 AD xb ee ff fRPP CPY [D ,xysp ] [D,IDX] AD xb fIfRfP CPY [ oprx16,xysp ] [IDX2] AD xb ee ff fIPRfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-68 REFERENCE MANUAL...
  • Page 129 Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. Undefined. Represents BCD carry. See table above. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 07 CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-69...
  • Page 130 04 04 rr 04 14 rr DBEQ X, rel9 04 05 rr 04 15 rr DBEQ Y, rel9 04 06 rr 04 16 rr DBEQ SP, rel9 04 07 rr 04 17 rr MOTOROLA INSTRUCTION GLOSSARY CPU12 6-70 REFERENCE MANUAL...
  • Page 131 04 24 rr 04 34 rr DBNE X, rel9 04 25 rr 04 35 rr DBNE Y, rel9 04 26 rr 04 36 rr DBNE SP, rel9 04 27 rr 04 37 rr CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-71...
  • Page 132 DEC oprx9,xysp IDX1 63 xb ff rPOw DEC oprx16,xysp IDX2 63 xb ee ff frPPw DEC [D ,xysp ] [D,IDX] 63 xb fIfrPw DEC [ oprx16,xysp ] [IDX2] 63 xb ee ff fIPrPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-72 REFERENCE MANUAL...
  • Page 133 Two’s complement overflow occurs if and only if (A) was $80 before the operation. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail DECA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-73...
  • Page 134 Two’s complement overflow occurs if and only if (B) was $80 before the operation. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail DECB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-74 REFERENCE MANUAL...
  • Page 135 Object Code Cycles Access Detail DES translates to... 1B 9F LEAS –1,SP Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-75...
  • Page 136 Condition Codes and Boolean Formulas: ∆ – – – – – – – Set if result is $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail MOTOROLA INSTRUCTION GLOSSARY CPU12 6-76 REFERENCE MANUAL...
  • Page 137 Condition Codes and Boolean Formulas: ∆ – – – – – – – Set if result is $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-77...
  • Page 138 Set if the result was > $FFFF; cleared otherwise. Undefined after di- vision by zero. Set if divisor was $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail EDIV ffffffffffO MOTOROLA INSTRUCTION GLOSSARY CPU12 6-78 REFERENCE MANUAL...
  • Page 139 Set if divisor was $0000; cleared otherwise. (Indicates division by zero.) Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail EDIVS 18 14 OffffffffffO CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-79...
  • Page 140 Source Form Address Mode Object Code Cycles Access Detail EMACS opr16a Special 18 12 hh ll ORROfffRRfWWP Notes: 1. opr16a is an extended address specification. Both X and Y point to source operands. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-80 REFERENCE MANUAL...
  • Page 141 18 1A xb ff ORPO EMAXD oprx16,xysp IDX2 18 1A xb ee ff OfRPP EMAXD [D ,xysp ] [D,IDX] 18 1A xb OfIfRfP EMAXD [ oprx16,xysp ] [IDX2] 18 1A xb ee ff OfIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-81...
  • Page 142 18 1E xb ff ORPWO EMAXM oprx16,xysp IDX2 18 1E xb ee ff OfRPWP EMAXM [D ,xysp ] [D,IDX] 18 1E xb OfIfRPW EMAXM [ oprx16,xysp ] [IDX2] 18 1E xb ee ff OfIPRPW MOTOROLA INSTRUCTION GLOSSARY CPU12 6-82 REFERENCE MANUAL...
  • Page 143 18 1B xb ff ORPO EMIND oprx16,xysp IDX2 18 1B xb ee ff OfRPP EMIND [D ,xysp ] [D,IDX] 18 1B xb OfIfRfP EMIND [ oprx16,xysp ] [IDX2] 18 1B xb ee ff OfIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-83...
  • Page 144 18 1F xb ff ORPWO EMINM oprx16,xysp IDX2 18 1F xb ee ff OfRPWP EMINM [D ,xysp ] [D,IDX] 18 1F xb OfIfRPW EMINM [ oprx16,xysp ] [IDX2] 18 1F xb ee ff OfIPRPW MOTOROLA INSTRUCTION GLOSSARY CPU12 6-84 REFERENCE MANUAL...
  • Page 145 Set if result is $00000000; cleared otherwise. Set if bit 15 of the result is set; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail EMUL CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-85...
  • Page 146 Set if result is $00000000; cleared otherwise. Set if bit 15 of the result is set; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail EMULS 18 13 MOTOROLA INSTRUCTION GLOSSARY CPU12 6-86 REFERENCE MANUAL...
  • Page 147 A8 xb EORA oprx9,xysp IDX1 A8 xb ff EORA oprx16,xysp IDX2 A8 xb ee ff frPP EORA [D ,xysp ] [D,IDX] A8 xb fIfrfP EORA [ oprx16,xysp ] [IDX2] A8 xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-87...
  • Page 148 EORB oprx9 , xysp IDX1 E8 xb ff EORB oprx16 , xysp IDX2 E8 xb ee ff frPP EORB [D ,xysp ] [D,IDX] E8 xb fIfrfP EORB [ oprx16,xysp ] [IDX2] E8 xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-88 REFERENCE MANUAL...
  • Page 149 Set if MSB of result is set; cleared otherwise. Set if result is $0000; cleared otherwise. Undefined. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ETBL oprx0_xysp 18 3F xb ORRffffffP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-89...
  • Page 150 16-bit registers differ- ently. Exchanges of D with A or B are ambiguous. Cases involving TMP2 and TMP3 are reserved for Motorola use, so some assemblers may not permit their use, but it is possible to generate these cases by using DC.B or DC.W assembler directives.
  • Page 151 X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0 Set if denominator was $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail FDIV 18 11 OffffffffffO CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-91...
  • Page 152 04 84 rr 04 94 rr IBEQ X, rel9 04 85 rr 04 95 rr IBEQ Y, rel9 04 86 rr 04 96 rr IBEQ SP, rel9 04 87 rr 04 97 rr MOTOROLA INSTRUCTION GLOSSARY CPU12 6-92 REFERENCE MANUAL...
  • Page 153 04 A4 rr 04 B4 rr IBNE X, rel9 04 A5 rr 04 B5 rr IBNE Y, rel9 04 A6 rr 04 B6 rr IBNE SP, rel9 04 A7 rr 04 B7 rr CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-93...
  • Page 154 X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0 Set if denominator was $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail IDIV 18 10 OffffffffffO MOTOROLA INSTRUCTION GLOSSARY CPU12 6-94 REFERENCE MANUAL...
  • Page 155 X15 • X14 • X13 • X12 •... • X3 • X2 • X1 • X0 Set if denominator was $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail IDIVS 18 15 OffffffffffO CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-95...
  • Page 156 INC oprx9,xysp IDX1 62 xb ff rPOw INC oprx16,xysp IDX2 62 xb ee ff frPPw INC [D ,xysp ] [D,IDX] 62 xb fIfrPw INC [ oprx16,xysp ] [IDX2] 62 xb ee ff fIPrPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-96 REFERENCE MANUAL...
  • Page 157 Two’s complement overflow occurs if and only if (A) was $7F before the operation. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail INCA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-97...
  • Page 158 Two’s complement overflow occurs if and only if (B) was $7F before the operation. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail INCB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-98 REFERENCE MANUAL...
  • Page 159 Object Code Cycles Access Detail INS translates to... 1B 81 LEAS 1,SP Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-99...
  • Page 160 Condition Codes and Boolean Formulas: ∆ – – – – – – – Set if result is $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail MOTOROLA INSTRUCTION GLOSSARY CPU12 6-100 REFERENCE MANUAL...
  • Page 161 Condition Codes and Boolean Formulas: ∆ – – – – – – – Set if result is $0000; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-101...
  • Page 162 05 xb JMP oprx9,xysp IDX1 05 xb ff JMP oprx16,xysp IDX2 05 xb ee ff fPPP JMP [D ,xysp ] [D,IDX] 05 xb fIfPPP JMP [ oprx16,xysp ] [IDX2] 05 xb ee ff fIfPPP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-102 REFERENCE MANUAL...
  • Page 163 JSR oprx9,xysp IDX1 15 xb ff PPPS JSR oprx16,xysp IDX2 15 xb ee ff fPPPS JSR [D ,xysp ] [D,IDX] 15 xb fIfPPPS JSR [ oprx16,xysp ] [IDX2] 15 xb ee ff fIfPPPS CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-103...
  • Page 164 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-104 REFERENCE MANUAL...
  • Page 165 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-105...
  • Page 166 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-106 REFERENCE MANUAL...
  • Page 167 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-107...
  • Page 168 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-108 REFERENCE MANUAL...
  • Page 169 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-109...
  • Page 170 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-110 REFERENCE MANUAL...
  • Page 171 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-111...
  • Page 172 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-112 REFERENCE MANUAL...
  • Page 173 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-113...
  • Page 174 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-114 REFERENCE MANUAL...
  • Page 175 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-115...
  • Page 176 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-116 REFERENCE MANUAL...
  • Page 177 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-117...
  • Page 178 – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LBRA rel16 18 20 qq rr OPPP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-118 REFERENCE MANUAL...
  • Page 179 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LBRN rel16 18 21 qq rr CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-119...
  • Page 180 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional MOTOROLA INSTRUCTION GLOSSARY CPU12 6-120 REFERENCE MANUAL...
  • Page 181 LBVS 18 29 V = 1 No Overflow LBVC 18 28 Simple LBEQ 18 27 Z = 1 r≠0 LBNE 18 26 Simple Always LBRA 18 20 — Never LBRN 18 21 Unconditional CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-121...
  • Page 182 A6 xb LDAA oprx9,xysp IDX1 A6 xb ff LDAA oprx16,xysp IDX2 A6 xb ee ff frPP LDAA [D ,xysp ] [D,IDX] A6 xb fIfrfP LDAA [ oprx16,xysp ] [IDX2] A6 xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-122 REFERENCE MANUAL...
  • Page 183 LDAB oprx9 , xysp IDX1 E6 xb ff LDAB oprx16 , xysp IDX2 E6 xb ee ff frPP LDAB [D ,xysp ] [D,IDX] E6 xb fIfrfP LDAB [ oprx16,xysp ] [IDX2] E6 xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-123...
  • Page 184 EC xb LDD oprx9,xysp IDX1 EC xb ff LDD oprx16,xysp IDX2 EC xb ee ff fRPP LDD [D ,xysp ] [D,IDX] EC xb fIfRfP LDD [ oprx16,xysp ] [IDX2] EC xb ee ff fIPRfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-124 REFERENCE MANUAL...
  • Page 185 EF xb LDS oprx9,xysp IDX1 EF xb ff LDS oprx16,xysp IDX2 EF xb ee ff fRPP LDS [D ,xysp ] [D,IDX] EF xb fIfRfP LDS [ oprx16,xysp ] [IDX2] EF xb ee ff fIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-125...
  • Page 186 EE xb LDX oprx9,xysp IDX1 EE xb ff LDX oprx16,xysp IDX2 EE xb ee ff fRPP LDX [D ,xysp ] [D,IDX] EE xb fIfRfP LDX [ oprx16,xysp ] [IDX2] EE xb ee ff fIPRfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-126 REFERENCE MANUAL...
  • Page 187 ED xb LDY oprx9,xysp IDX1 ED xb ff LDY oprx16,xysp IDX2 ED xb ee ff fRPP LDY [D ,xysp ] [D,IDX] ED xb fIfRfP LDY [ oprx16,xysp ] [IDX2] ED xb ee ff fIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-127...
  • Page 188 LEAS oprx9,xysp IDX1 1B xb ff LEAS oprx16,xysp IDX2 1B xb ee ff Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-128 REFERENCE MANUAL...
  • Page 189 LEAX oprx9,xysp IDX1 1A xb ff LEAX oprx16,xysp IDX2 1A xb ee ff Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-129...
  • Page 190 LEAY oprx9,xysp IDX1 19 xb ff LEAY oprx16,xysp IDX2 19 xb ee ff Notes: 1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-130 REFERENCE MANUAL...
  • Page 191 LSL oprx9,xysp IDX1 68 xb ff rPOw LSL oprx16,xysp IDX2 68 xb ee ff frPPw LSL [D ,xysp ] [D,IDX] 68 xb fIfrPw LSL [ oprx16,xysp ] [IDX2] 68 xb ee ff fIPrPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-131...
  • Page 192 (for values of N and C after the shift). Set if the LSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSLA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-132 REFERENCE MANUAL...
  • Page 193 (for values of N and C after the shift). Set if the LSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSLB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-133...
  • Page 194 (for values of N and C after the shift). Set if the MSB of D was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSLD MOTOROLA INSTRUCTION GLOSSARY CPU12 6-134 REFERENCE MANUAL...
  • Page 195 LSR oprx9,xysp IDX1 64 xb ff rPOw LSR oprx16,xysp IDX2 64 xb ee ff frPPw LSR [D ,xysp ] [D,IDX] 64 xb fIfrPw LSR [ oprx16,xysp ] [IDX2] 64 xb ee ff fIPrPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-135...
  • Page 196 (for values of N and C after the shift). Set if the LSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSRA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-136 REFERENCE MANUAL...
  • Page 197 (for values of N and C after the shift). Set if the LSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSRB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-137...
  • Page 198 Set if, after the shift operation, C is set; cleared otherwise. Set if the LSB of D was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail LSRD MOTOROLA INSTRUCTION GLOSSARY CPU12 6-138 REFERENCE MANUAL...
  • Page 199 18 18 xb ff OrPO MAXA oprx16,xysp IDX2 18 18 xb ee ff OfrPP MAXA [D ,xysp ] [D,IDX] 18 18 xb OfIfrfP MAXA [ oprx16,xysp ] [IDX2] 18 18 xb ee ff OfIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-139...
  • Page 200 18 1C xb ff OrPwO MAXM oprx16,xysp IDX2 18 1C xb ee ff OfrPwP MAXM [D ,xysp ] [D,IDX] 18 1C xb OfIfrPw MAXM [ oprx16,xysp ] [IDX2] 18 1C xb ee ff OfIPrPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-140 REFERENCE MANUAL...
  • Page 201 – – – H, N, Z, V, and C may be altered by this instruction. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail Special RRfOw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-141...
  • Page 202 18 19 xb ff OrPO MINA oprx16,xysp IDX2 18 19 xb ee ff OfrPP MINA [D ,xysp ] [D,IDX] 18 19 xb OfIfrfP MINA [ oprx16,xysp ] [IDX2] 18 19 xb ee ff OfIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-142 REFERENCE MANUAL...
  • Page 203 18 1D xb ff OrPwO MINM oprx16,xysp IDX2 18 1D xb ee ff OfrPwP MINM [D ,xysp ] [D,IDX] 18 1D xb OfIfrPw MINM [ oprx16,xysp ] [IDX2] 18 1D xb ee ff OfIPrPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-143...
  • Page 204 MOVB oprx0_xysp, opr16a IDX–EXT 18 0D xb hh ll OrPwP MOVB oprx0_xysp, oprx0_xysp IDX–IDX 18 0A xb xb OrPwO Notes: 1. The first operand in the source code statement specifies the source for the move. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-144 REFERENCE MANUAL...
  • Page 205 MOVW oprx0_xysp, opr16a IDX–EXT 18 05 xb hh ll ORPWP MOVW oprx0_xysp, oprx0_xysp IDX–IDX 18 02 xb xb ORPWO Notes: 1. The first operand in the source code statement specifies the source for the move. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-145...
  • Page 206 – – – Set if bit 7 of the result (B bit 7) is set; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail MOTOROLA INSTRUCTION GLOSSARY CPU12 6-146 REFERENCE MANUAL...
  • Page 207 NEG oprx9,xysp IDX1 60 xb ff rPOw NEG oprx16,xysp IDX2 60 xb ee ff frPPw NEG [D ,xysp ] [D,IDX] 60 xb fIfrPw NEG [ oprx16,xysp ] [IDX2] 60 xb ee ff fIPrPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-147...
  • Page 208 Set if there is a borrow in the implied subtraction from zero; cleared oth- erwise. Set in all cases except when (A) = $00. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail NEGA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-148 REFERENCE MANUAL...
  • Page 209 Set if there is a borrow in the implied subtraction from zero; cleared oth- erwise. Set in all cases except when (B) = $00. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail NEGB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-149...
  • Page 210 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail MOTOROLA INSTRUCTION GLOSSARY CPU12 6-150 REFERENCE MANUAL...
  • Page 211 AA xb ORAA oprx9,xysp IDX1 AA xb ff ORAA oprx16,xysp IDX2 AA xb ee ff frPP ORAA [D ,xysp ] [D,IDX] AA xb fIfrfP ORAA [ oprx16,xysp ] [IDX2] AA xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-151...
  • Page 212 ORAB oprx9 , xysp IDX1 EA xb ff ORAB oprx16 , xysp IDX2 EA xb ee ff frPP ORAB [D ,xysp ] [D,IDX] EA xb fIfrfP ORAB [ oprx16,xysp ] [IDX2] EA xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-152 REFERENCE MANUAL...
  • Page 213 The X interrupt mask cannot be set by any software instruction. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ORCC # opr8i 14 ii CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-153...
  • Page 214 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PSHA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-154 REFERENCE MANUAL...
  • Page 215 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PSHB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-155...
  • Page 216 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PSHC MOTOROLA INSTRUCTION GLOSSARY CPU12 6-156 REFERENCE MANUAL...
  • Page 217 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PSHD CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-157...
  • Page 218 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PSHX MOTOROLA INSTRUCTION GLOSSARY CPU12 6-158 REFERENCE MANUAL...
  • Page 219 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PSHY CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-159...
  • Page 220 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PULA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-160 REFERENCE MANUAL...
  • Page 221 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PULB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-161...
  • Page 222 X bit set, leave it cleared, or change it from one to zero, but it can only be set by a reset or by recognition of an XIRQ interrupt. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PULC MOTOROLA INSTRUCTION GLOSSARY CPU12 6-162 REFERENCE MANUAL...
  • Page 223 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PULD CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-163...
  • Page 224 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PULX MOTOROLA INSTRUCTION GLOSSARY CPU12 6-164 REFERENCE MANUAL...
  • Page 225 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail PULY CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-165...
  • Page 226 $FF separator at the end of the rule list. Index register Y points to the base address for the fuzzy inputs and fuzzy outputs. The value in Y does not change during execution. MOTOROLA INSTRUCTION GLOSSARY CPU12...
  • Page 227 1. The 3-cycle loop in parentheses is executed once for each element in the rule list. When an interrupt occurs, there is a 2-cycle exit sequence, a 4-cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-167...
  • Page 228 When execution is complete, Y points to the last weighting factor used. When weighting is not used (C = 0), Y is not changed. MOTOROLA INSTRUCTION GLOSSARY CPU12...
  • Page 229 When an interrupt occurs, there is a 2-cycle exit sequence, a 4- cycle re-entry sequence, then execution resumes with a prefetch of the last antecedent or consequent being pro- cessed at the time of the interrupt. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-169...
  • Page 230 ROL oprx9,xysp IDX1 65 xb ff rPOw ROL oprx16,xysp IDX2 65 xb ee ff frPPw ROL [D ,xysp ] [D,IDX] 65 xb fIfrPw ROL [ oprx16,xysp ] [IDX2] 65 xb ee ff fIPrPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-170 REFERENCE MANUAL...
  • Page 231 (for values of N and C after the shift). Set if the MSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ROLA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-171...
  • Page 232 (for values of N and C after the shift). Set if the MSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail ROLB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-172 REFERENCE MANUAL...
  • Page 233 ROR oprx9,xysp IDX1 66 xb ff rPOw ROR oprx16,xysp IDX2 66 xb ee ff frPPw ROR [D ,xysp ] [D,IDX] 66 xb fIfrPw ROR [ oprx16,xysp ] [IDX2] 66 xb ee ff fIPrPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-173...
  • Page 234 (for values of N and C after the shift). Set if the LSB of A was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail RORA MOTOROLA INSTRUCTION GLOSSARY CPU12 6-174 REFERENCE MANUAL...
  • Page 235 (for values of N and C after the shift). Set if the LSB of B was set before the shift; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail RORB CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-175...
  • Page 236 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail uUnPPP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-176 REFERENCE MANUAL...
  • Page 237 XIRQ interrupt. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail uUUUUPPP (with interrupt pending) uUUUUVfPPP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-177...
  • Page 238 Condition Codes and Boolean Formulas: – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail UfPPP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-178 REFERENCE MANUAL...
  • Page 239 Set if the absolute value of B is larger than the absolute value of A; cleared otherwise. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 16 CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-179...
  • Page 240 A2 xb SBCA oprx9,xysp IDX1 A2 xb ff SBCA oprx16,xysp IDX2 A2 xb ee ff frPP SBCA [D ,xysp ] [D,IDX] A2 xb fIfrfP SBCA [ oprx16,xysp ] [IDX2] A2 xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-180 REFERENCE MANUAL...
  • Page 241 SBCB oprx9 , xysp IDX1 E2 xb ff SBCB oprx16 , xysp IDX2 E2 xb ee ff frPP SBCB [D ,xysp ] [D,IDX] E2 xb fIfrfP SBCB [ oprx16,xysp ] [IDX2] E2 xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-181...
  • Page 242 Condition Codes and Boolean Formulas: – – – – – – – 1; Set. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail SEC translates to... 14 01 ORCC #$01 MOTOROLA INSTRUCTION GLOSSARY CPU12 6-182 REFERENCE MANUAL...
  • Page 243 Condition Codes and Boolean Formulas: – – – – – – – 1; Set. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail SEI translates to... 14 10 ORCC #$10 CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-183...
  • Page 244 Condition Codes and Boolean Formulas: – – – – – – – 1; Set. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail SEV translates to... 14 02 ORCC #$02 MOTOROLA INSTRUCTION GLOSSARY CPU12 6-184 REFERENCE MANUAL...
  • Page 245 SEX B,X SEX CCR,X sex:A ⇒ Y sex:B ⇒ Y sex:CCR ⇒ Y SEX A,Y SEX B,Y SEX CCR,Y sex:A ⇒ SP sex:B ⇒ SP sex:CCR ⇒ SP SEX A,SP SEX B,SP SEX CCR,SP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-185...
  • Page 246 6A xb STAA oprx9,xysp IDX1 6A xb ff STAA oprx16,xysp IDX2 6A xb ee ff STAA [D ,xysp ] [D,IDX] 6A xb PIfPw STAA [ oprx16,xysp ] [IDX2] 6A xb ee ff PIPPw MOTOROLA INSTRUCTION GLOSSARY CPU12 6-186 REFERENCE MANUAL...
  • Page 247 STAB oprx9 , xysp IDX1 6B xb ff STAB oprx16 , xysp IDX2 6B xb ee ff STAB [D ,xysp ] [D,IDX] 6B xb PIfPw STAB [ oprx16,xysp ] [IDX2] 6B xb ee ff PIPPw CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-187...
  • Page 248 6C xb STD oprx9,xysp IDX1 6C xb ff STD oprx16,xysp IDX2 6C xb ee ff STD [D ,xysp ] [D,IDX] 6C xb PIfPW STD [ oprx16,xysp ] [IDX2] 6C xb ee ff PIPPW MOTOROLA INSTRUCTION GLOSSARY CPU12 6-188 REFERENCE MANUAL...
  • Page 249 – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail STOP (entering STOP) 18 3E OOSSSfSsf (exiting STOP) VfPPP (continue) (if STOP disabled) CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-189...
  • Page 250 6F xb STS oprx9,xysp IDX1 6F xb ff STS oprx16,xysp IDX2 6F xb ee ff STS [D ,xysp ] [D,IDX] 6F xb PIfPW STS [ oprx16,xysp ] [IDX2] 6F xb ee ff PIPPW MOTOROLA INSTRUCTION GLOSSARY CPU12 6-190 REFERENCE MANUAL...
  • Page 251 6E xb STX oprx9,xysp IDX1 6E xb ff STX oprx16,xysp IDX2 6E xb ee ff STX [D ,xysp ] [D,IDX] 6E xb PIfPW STX [ oprx16,xysp ] [IDX2] 6E xb ee ff PIPPW CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-191...
  • Page 252 6D xb STY oprx9,xysp IDX1 6D xb ff STY oprx16,xysp IDX2 6D xb ee ff STY [D ,xysp ] [D,IDX] 6D xb PIfPW STY [ oprx16,xysp ] [IDX2] 6D xb ee ff PIPPW MOTOROLA INSTRUCTION GLOSSARY CPU12 6-192 REFERENCE MANUAL...
  • Page 253 A0 xb SUBA oprx9,xysp IDX1 A0 xb ff SUBA oprx16,xysp IDX2 A0 xb ee ff frPP SUBA [D ,xysp ] [D,IDX] A0 xb fIfrfP SUBA [ oprx16,xysp ] [IDX2] A0 xb ee ff fIPrfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-193...
  • Page 254 SUBB oprx9 , xysp IDX1 E0 xb ff SUBB oprx16 , xysp IDX2 E0 xb ee ff frPP SUBB [D ,xysp ] [D,IDX] E0 xb fIfrfP SUBB [ oprx16,xysp ] [IDX2] E0 xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-194 REFERENCE MANUAL...
  • Page 255 A3 xb SUBD oprx9,xyssp IDX1 A3 xb ff SUBD oprx16,xysp IDX2 A3 xb ee ff fRPP SUBD [D ,xysp ] [D,IDX] A3 xb fIfRfP SUBD [ oprx16,xysp ] [IDX2] A3 xb ee ff fIPRfP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-195...
  • Page 256 Object Code Cycles Access Detail VSPSSPSsP Notes: 1. The CPU also uses the SWI processing sequence for hardware interrupts and unimplemented opcode traps. A variation of the sequence (VfPPP) is used for resets. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-196 REFERENCE MANUAL...
  • Page 257 Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 0E CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-197...
  • Page 258 XIRQ interrupt. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TAP translates to... B7 02 TFR A,CCR MOTOROLA INSTRUCTION GLOSSARY CPU12 6-198 REFERENCE MANUAL...
  • Page 259 Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail 18 0F CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-199...
  • Page 260 04 44 rr 04 54 rr TBEQ X, rel9 04 45 rr 04 55 rr TBEQ Y, rel9 04 46 rr 04 56 rr TBEQ SP, rel9 04 47 rr 04 57 rr MOTOROLA INSTRUCTION GLOSSARY CPU12 6-200 REFERENCE MANUAL...
  • Page 261 Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. Undefined. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TBL oprx0_xysp 18 3D xb OrrffffP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-201...
  • Page 262 04 64 rr 04 74 rr TBNE X, rel9 04 65 rr 04 75 rr TBNE Y, rel9 04 66 rr 04 76 rr TBNE SP, rel9 04 67 rr 04 77 rr MOTOROLA INSTRUCTION GLOSSARY CPU12 6-202 REFERENCE MANUAL...
  • Page 263 The order in which transfers between 8-bit and 16- bit registers are specified affects the high byte of the 16-bit registers dif- ferently. Cases involving TMP2 and TMP3 are reserved for Motorola use, so some assemblers may not permit their use. It is possible to gen- erate these cases by using DC.B or DC.W assembler directives.
  • Page 264 – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TPA translates to... B7 20 TFR CCR,A MOTOROLA INSTRUCTION GLOSSARY CPU12 6-204 REFERENCE MANUAL...
  • Page 265 Object Code Cycles Access Detail TRAP trapnum $18 tn OfVSPSSPSsP Notes: 1. The value tn represents an unimplemented page 2 opcode in either of the two ranges $30 to $39 or $40 to $FF. CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-205...
  • Page 266 E7 xb TST oprx9,xysp IDX1 E7 xb ff TST oprx16,xysp IDX2 E7 xb ee ff frPP TST [D ,xysp ] [D,IDX] E7 xb fIfrfP TST [ oprx16,xysp ] [IDX2] E7 xb ee ff fIPrfP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-206 REFERENCE MANUAL...
  • Page 267 Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TSTA CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-207...
  • Page 268 Set if MSB of result is set; cleared otherwise. Set if result is $00; cleared otherwise. 0; Cleared. 0; Cleared. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TSTB MOTOROLA INSTRUCTION GLOSSARY CPU12 6-208 REFERENCE MANUAL...
  • Page 269 – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TSX translates to... B7 75 TFR SP,X CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-209...
  • Page 270 – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TSY translates to... B7 76 TFR SP,Y MOTOROLA INSTRUCTION GLOSSARY CPU12 6-210 REFERENCE MANUAL...
  • Page 271 – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TXS translates to... B7 57 TFR X,SP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-211...
  • Page 272 – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail TYS translates to... B7 67 TFR Y,SP MOTOROLA INSTRUCTION GLOSSARY CPU12 6-212 REFERENCE MANUAL...
  • Page 273 I mask bit (and the X mask bit, if the interrupt was XIRQ) to be set as the interrupt vector is fetched. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail WAI (before interrupt) OSSSfSsf (when interrupt comes) VfPPP CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-213...
  • Page 274 Object Code Cycles Access Detail Special See note 18 3C Off(frrfffff)O (add if interrupted) SSSUUUrr Notes: 1. The 8-cycle sequence in parentheses represents the loop for one iteration of SOP and SOW accumulation. MOTOROLA INSTRUCTION GLOSSARY CPU12 6-214 REFERENCE MANUAL...
  • Page 275 – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail XGDX translates to... B7 C5 EXG D,X CPU12 INSTRUCTION GLOSSARY MOTOROLA REFERENCE MANUAL 6-215...
  • Page 276 – – – – – – – – None affected. Addressing Modes, Machine Code, and Execution Times: Source Form Address Mode Object Code Cycles Access Detail XGDY translates to... B7 C6 EXG D,Y MOTOROLA INSTRUCTION GLOSSARY CPU12 6-216 REFERENCE MANUAL...
  • Page 277: Exception Processing

    The CPU12 can handle up to 64 exception vectors, but the number actually used var- ies from device to device, and some vectors are reserved for Motorola use. Refer to device documentation for more information.
  • Page 278: Exception Priority

    CPU12. The CPU fetches a vector determined by the type of reset that has occurred, jumps to the address pointed to by the vector, and begins to execute code at that address. MOTOROLA EXCEPTION PROCESSING CPU12...
  • Page 279 The higher the vector address, the higher the priority of the interrupt. Typically, a de- vice integration module incorporates logic that can give one maskable source priority over other maskable sources. CPU12 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL...
  • Page 280 At the end of the interrupt service routine, an RTI instruction restores context from the stacked registers, and normal program execution resumes. MOTOROLA EXCEPTION PROCESSING CPU12 REFERENCE MANUAL...
  • Page 281 This differs from the M68HC11 illegal opcode interrupt, which uses the ad- dress of an illegal opcode as the return address. In the CPU12, the stacked return ad- dress can be used to calculate the address of the unimplemented opcode for software- controlled traps. CPU12 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL...
  • Page 282: Software Interrupt Instruction

    Fetches start at the address pointed to by the reset vector. When the fetches are completed, exception processing ends, and the CPU starts ex- ecuting the instruction at the head of the instruction queue. MOTOROLA EXCEPTION PROCESSING CPU12...
  • Page 283: Exception Processing Flow Diagram

    Set I bit If XIRQ, set X bit 9.2 - P Fetch program word 9.1 - P Fetch program word Finish filling instruction queue Finish filling instruction queue CPU12EXPFLOW Figure 7-2 Exception Processing Flow Diagram CPU12 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL...
  • Page 284 Cycle 9.1/9.2 is the third of three program word fetches that refill the instruction queue. It is the last cycle of exception processing. After this cycle the CPU starts executing the first cycle of the instruction at the head of the instruction queue. MOTOROLA EXCEPTION PROCESSING CPU12...
  • Page 285: Development And Debug Support

    During reset, the pins are used as mode-select input sig- nals MODA and MODB. After reset, information on the pins does not become valid un- til an instruction reaches queue stage 2. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 286: Queue Status Signal Timing

    Advance queue and load from bus Advance queue and load from latch Execution Start Mnemonic Meaning (capture at E fall) — No start Start interrupt sequence Start even instruction Start odd instruction MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 REFERENCE MANUAL...
  • Page 287 2 of the opcode map as a special 1-byte, 1-cycle instruction, except that interrupts are not recognized at the boundary between the prebyte and the rest of the instruction. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 288: Implementing Queue Reconstruction

    8.3.1.2 fetch_add, fetch_dat Registers These registers buffer address and data for information that was fetched before the queue was ready to advance. MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 REFERENCE MANUAL...
  • Page 289 However, the cycle to fetch the next word of program infor- mation has already started and the data is on its way. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 290: Background Debug Mode

    ENBDM is cleared by another debugging command. Second, BDM must be activated to map the ROM and BDM control registers to addresses $FF00 to $FFFF and put the MCU in back- ground mode. MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 REFERENCE MANUAL...
  • Page 291 Ten target E-cycles later, the target senses the bit level on the BKGD pin. The host can drive high during host-to-target transmission to speed up rising edges, because the target does not drive the pin during this time. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 292: Bdm Host To Target Serial Bit Timing

    R-C RISE BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN CPU12 BDM TH TIM 1 Figure 8-3 BDM Target to Host Serial Bit Timing (Logic 1) MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 REFERENCE MANUAL...
  • Page 293: Bdm Target To Host Serial Bit Timing (Logic 0)

    BACKGROUND, do not require the CPU to be in BDM mode for ex- ecution. The control logic uses CPU dead cycles to execute these instructions. If a dead cycle cannot be found within 128 cycles, the control logic steals cycles from the CPU. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 294 CPU oper- ation. However, if an operation requires multiple cycles, CPU clocks are frozen until the operation is complete. MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 8-10...
  • Page 295 BDM firmware to execute commands. The registers can be accessed by means of the hardware READ_BD and WRITE_BD commands, but must not be written during BDM operation. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL 8-11...
  • Page 296 TRACE — Trace Flag Shows when tracing is enabled. NOTE Execute a TRACE1 command to enable instruction tagging. Do not attempt to write TRACE directly. 0 = Tracing not enabled 1 = Tracing active MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 8-12 REFERENCE MANUAL...
  • Page 297: Instruction Tagging

    ECLK performs the indicated function. Tagging is allowed in all modes. Tagging is disabled when BDM becomes active. Table 8-5 Tag Pin Function TAGHI TAGLO No Tag Low Byte High Byte Both Bytes CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL 8-13...
  • Page 298: Breakpoints

    SWI. When BDM is forced, the CPU executes a BGND instruction. However, because these operations are not part of the normal flow of instruction execution, the control program must keep track of the actual breakpoint address. MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12...
  • Page 299 Registers can be used to match the high and low bytes of addresses for single and dual breakpoints, to match data for single breakpoints, or to do both functions. Use of the registers is generally determined by control bit settings. CPU12 DEVELOPMENT AND DEBUG SUPPORT MOTOROLA REFERENCE MANUAL 8-15...
  • Page 300 MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 8-16 REFERENCE MANUAL...
  • Page 301: Introduction

    By incorporating fuzzy logic support into a high-volume, general-pur- pose microcontroller product family, Motorola has made fuzzy logic available for a huge base of applications. 9.2 Fuzzy Logic Basics This is an overview of basic fuzzy logic concepts.
  • Page 302 Choosing a periodic rate for a fuzzy control system is the same as it would be for a conventional control system. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
  • Page 303: Block Diagram Of A Fuzzy Logic System

    $40 is stored to a RAM location, and is called a fuzzy input (in this case, the fuzzy input for “temperature is warm”). There is a RAM location for each fuzzy input (for each label of each system input). CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 304: Fuzzification Using Membership Functions

    The end result of the fuzzification step is a table of fuzzy inputs representing current system conditions. MOTOROLA FUZZY LOGIC SUPPORT CPU12 REFERENCE MANUAL...
  • Page 305 There also must be a way to know when the last rule in the system has been reached. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 306 One method of organization is to have a fixed number of rules with a specific number of antecedents and consequents. A second method, employed in Motorola Freeware M68HC11 kernels, is to mark the end of the rule list with a reserved value, and use a bit in the pointers to distinguish antecedents from consequents.
  • Page 307: Example Inference Kernel

    Lines 9 and 10 form a loop to fuzzify the seven labels of the second system input. When the program drops to line 11, the Y index register is pointing at the next location after the last fuzzy input, which is the first fuzzy output in this system. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 308: Fuzzy Inference Engine

    $FF character is found. For a system of 17 rules with two ante- cedents and one consequent each, the REV instruction takes 259 cycles, but it is in- terruptible so it does not cause a long interrupt latency. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
  • Page 309: Mem Instruction Details

    Typically, there are three to seven labels per system input, but there is no practical restriction on this number as far as the fuzzification step is concerned. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 310: Defining A Normal Membership Function

    CPU processes. It is common for several internal functions to take place during a single CPU cycle (for example, in cycle 2, two 8-bit subtractions take place and a flag is set based on the results). MOTOROLA FUZZY LOGIC SUPPORT CPU12...
  • Page 311: Mem Instruction Flow Diagram

    $FF as far as the right sloping side is concerned. 4a decides if the value is left of the right sloping side (Grade = $FF), or on the sloping portion of the right side of the trapezoid (Grade = Grade_2). 4b could still override this tentative value in grade. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-11...
  • Page 312: Abnormal Membership Function Case 1

    If point_1 was to the right of point_2, flag_d12n would force the result to be $00 for all input values. In fact, flag_d12n always limits the region of interest to the space greater than or equal to point_1 and less than or equal to point_2. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
  • Page 313: Rev, Revw Instruction Details

    One uses 8-bit offsets in the encoded rules, while the other uses full 16-bit addresses. This affects the size of the rule data structure and execution time. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-13...
  • Page 314 A is automatically set to $FF when the instruction detects the $FE marker character between the last consequent of the previous rule, and the first antecedent of a new rule. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
  • Page 315 (refer to SECTION 6 INSTRUCTION GLOSSA- for details). Lower case letters indicate a cycle where 8-bit or no data is transferred. Upper case letters indicate cycles where 16-bit or no data is transferred. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-15...
  • Page 316: Rev Instruction Flow Diagram

    A = A (no change to A) = $FF (end of rules)? 7.0 - O Read program word if $3A misaligned REV INST FLOW Figure 9-9 REV Instruction Flow Diagram MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-16 REFERENCE MANUAL...
  • Page 317 During cycle 5.0, a new rule byte is read unless this is the last loop pass, and R $FF (marking the end of the rule list). This new rule byte will not be used until cycle 4.0 of the next pass through the loop. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-17...
  • Page 318 $FFFE, and the end of the last rule is marked by the reserved 16-bit value $FFFF. Since $FFFE and $FFFF correspond to the addresses of the reset vector, there would never be a fuzzy input or output at either of these locations. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
  • Page 319 (weighted) for the current rule. If the current truth value is larger, it is written over the previous value in the fuzzy output. After all rules have been evaluated, the fuzzy output contains the truth value for the most-true rule that referenced that fuzzy output. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-19...
  • Page 320 (refer to SECTION 6 IN- STRUCTION GLOSSARY for details). Lower case letters indicate a cycle where 8-bit or no data is transferred. Upper case letters indicate cycles where 16-bit data could be transferred. MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-20 REFERENCE MANUAL...
  • Page 321: Revw Instruction Flow Diagram

    Adjust PC to point at next instruction 8.2 - f If C = 1 (weights enabled), Y = TMP2 + 1 Finish multiply REVW INST FLW Figure 9-10 REVW Instruction Flow Diagram CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-21...
  • Page 322: Wav Instruction Details

    The WAV instruction performs weighted average calculations used in defuzzification. The pseudo-instruction wavr is used to resume an interrupted weighted average op- eration. WAV calculates the numerator and denominator sums using: ∑ System Output --------------------- - ∑ MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-22 REFERENCE MANUAL...
  • Page 323 PC is ad- justed again as it was for the first interrupt. WAV can be interrupted any number of times, and additional WAV instructions can be executed while a WAV instruction is in- terrupted. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-23...
  • Page 324 2.1 through 6.1 plus 7.0 through 11.0 plus 4.0 through 6.0 plus the exit 7.1 through 9.1. This is a worst-case total of 17 cycles. MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-24...
  • Page 325: Wav And Wavr Instruction Flow Diagram

    12.0 - O Read program word if $3C misaligned Adjust PC to point at next instruction Y : D = TMP3 : TMP2; X = TMP1 WAV INST FLOW Figure 9-11 WAV and wavr Instruction Flow Diagram CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-25...
  • Page 326: Custom Fuzzy Logic Programming

    The excessive size to specify tabular member- ship functions makes them impractical for most microcontroller-based fuzzy systems. The CPU12 instruction set includes two instructions (TBL and ETBL) for lookup and interpolation of compressed tables. MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-26...
  • Page 327 The table is entered with the x-coordinate of the desired point to lookup in the A accumulator. When the table is exited, the corresponding y-value is in the A accumulator. Figure 9-12 shows one way to work with this type of table. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-27...
  • Page 328: Endpoint Table Handling

    It makes intuitive sense that the exact shape of a membership function is much less important than the fact that it has gradual boundaries. MOTOROLA FUZZY LOGIC SUPPORT CPU12...
  • Page 329 There are two main areas where other CPU12 instructions can help with custom de- fuzzification routines. The first case is working with operands that are more than eight bits. The second case involves using an entirely different approach than weighted av- erage of singletons. CPU12 FUZZY LOGIC SUPPORT MOTOROLA REFERENCE MANUAL 9-29...
  • Page 330 8-MHz cycles. The EMACS instruction uses 16-bit operands and accumulates the result in a 32-bit memory location, taking only twelve 8-MHz cycles per iteration, including accessing all operands from memory and storing the result to memory. MOTOROLA FUZZY LOGIC SUPPORT CPU12 9-30...
  • Page 331: Expansion System Description

    EEPROM. The program window al- ways occupies the 16-Kbyte space from $8000 to $BFFF. Data and extra windows can vary in size and location. CPU12 MEMORY EXPANSION MOTOROLA REFERENCE MANUAL 10-1...
  • Page 332 $FF00 to $FF06. The BDM ROM replaces the reg- ular system vectors while BDM is active, but BDM resources are not in the memory map during normal execution of application programs. MOTOROLA MEMORY EXPANSION CPU12...
  • Page 333: Call And Return From Call Instructions

    Since the return operation is implemented as a single uninterruptable CPU instruction, the RTC can be executed from anywhere in memory, including from a different page of extended memory in the overlay window. CPU12 MEMORY EXPANSION MOTOROLA REFERENCE MANUAL 10-3...
  • Page 334: Address Lines For Expansion Memory

    DPAGE holds the page select for the data overlay, and EPAGE holds the page select for the extra page. The CPU12 manipu- lates the PPAGE register directly, so it will always be eight bits or less in devices that MOTOROLA MEMORY EXPANSION CPU12...
  • Page 335: Using Chip-Select Circuits

    Enables (1) or disables (0) the CSP0 chip select. The default is enabled. This allows CSP0 to be used to select an external memory that includes the reset vector and start- up initialization programs. CPU12 MEMORY EXPANSION MOTOROLA REFERENCE MANUAL 10-5...
  • Page 336 10.5.2 Data Expansion Chip Select Controls The data chip select (CSD) has four associated control bits. 10.5.2.1 CSDE Control Bit Enables (1) or disables (0) the CSD chip select. The default is disabled. MOTOROLA MEMORY EXPANSION CPU12 10-6 REFERENCE MANUAL...
  • Page 337: System Notes

    10.6 System Notes The expansion overlay windows are specialized for specific application uses, but there are no restrictions on the use of these memory spaces. Motorola MCUs have a mem- ory-mapped architecture in which all memory resources are treated equally. Although it is possible to execute programs in paged external memory in the data and extra overlay areas, it is less convenient than using the program overlay area.
  • Page 338 MOTOROLA MEMORY EXPANSION CPU12 10-8 REFERENCE MANUAL...
  • Page 339: A.1 Instruction Set Summary

    TBNE. The first digit of the instruction postbyte corresponds to the columns of the ta- ble. The second digit of the postbyte corresponds to the rows. The body of the table shows actions caused by the postbyte. CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL...
  • Page 340 C3 jj kk – – Add 16-Bit to D (A:B) D3 dd F3 hh ll E3 xb IDX1 E3 xb ff IDX2 E3 xb ee ff [D,IDX] E3 xb [IDX2] E3 xb ee ff MOTOROLA INSTRUCTION REFERENCE CPU12 REFERENCE MANUAL...
  • Page 341 – – – – – – (N ⊕ V) = 0) (signed) (if Z BHI rel Branch if Higher 22 rr – – – – – – – – (if C Z = 0) (unsigned) CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL...
  • Page 342 0C xb ee ff mm (SP) – 2 ⇒ SP; BSR rel 07 rr – – – – – – – – ⇒ M :RTN (SP) (SP+1) Subroutine address ⇒ PC Branch to Subroutine MOTOROLA INSTRUCTION REFERENCE CPU12 REFERENCE MANUAL...
  • Page 343 (B) – (M) C1 ii – – Compare Accumulator B with Memory D1 dd F1 hh ll E1 xb IDX1 E1 xb ff IDX2 E1 xb ee ff [D,IDX] E1 xb [IDX2] E1 xb ee ff CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL...
  • Page 344 – – – – – – If (cntr) not = 0, then Branch; (9-bit) else Continue to next instruction Decrement Counter and Branch if ≠ 0 (cntr = A, B, D, X, Y, or SP) MOTOROLA INSTRUCTION REFERENCE CPU12 REFERENCE MANUAL...
  • Page 345 ∆ ∆ EMUL – – – 16 × 16 Bit Multiply (unsigned) (D) × (Y) ⇒ Y:D – – ∆ ∆ ∆ EMULS 18 13 – – – 16 × 16 Bit Multiply (signed) CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL...
  • Page 346 – – – 16 × 16 Bit Integer Divide (unsigned) (D) ÷ (X) ⇒ X; r ⇒ D – – ∆ ∆ ∆ ∆ IDIVS 18 15 – – 16 × 16 Bit Integer Divide (signed) MOTOROLA INSTRUCTION REFERENCE CPU12 REFERENCE MANUAL...
  • Page 347 Long Branch if Plus (if N = 0) 18 2A qq rr – – – – – – – – LBRA rel Long Branch Always (if 1=1) 18 20 qq rr – – – – – – – – CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL...
  • Page 348 ED xb ee ff Effective Address ⇒ SP LEAS opr 1B xb – – – – – – – – Load Effective Address into SP IDX1 1B xb ff IDX2 1B xb ee ff MOTOROLA INSTRUCTION REFERENCE CPU12 A-10 REFERENCE MANUAL...
  • Page 349 A = current crisp input value; X points at 4-byte data structure that de- scribes a trapezoidal membership function (P1, P2, S1, S2); Y points at fuzzy input (RAM location). See instruction details for special cases. CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-11...
  • Page 350 EA xb ee ff [D,IDX] EA xb [IDX2] EA xb ee ff M ⇒ CCR ⇑ ⇑ ⇑ ⇑ ⇑ ⇑ ⇑ ORCC opr (CCR) 14 ii – Logical OR CCR with Memory MOTOROLA INSTRUCTION REFERENCE CPU12 A-12 REFERENCE MANUAL...
  • Page 351 Y. Each rule output is an 8- bit offset from the base address in Y. $FE separates rule inputs from rule outputs. $FF terminates the rule list. REV may be interrupted. CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-13...
  • Page 352 – – – – – – (SP) (SP+1) (SP) + 2 ⇒ SP Return from Subroutine (A) – (B) ⇒ A – – ∆ ∆ ∆ ∆ 18 16 – – Subtract B from A MOTOROLA INSTRUCTION REFERENCE CPU12 A-14 REFERENCE MANUAL...
  • Page 353 ∆ STD opr 5C dd – – – Store Double Accumulator 7C hh ll 6C xb IDX1 6C xb ff IDX2 6C xb ee ff [D,IDX] 6C xb [IDX2] 6C xb ee ff CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-15...
  • Page 354 C0 ii – – Subtract Memory from Accumulator B D0 dd F0 hh ll E0 xb IDX1 E0 xb ff IDX2 E0 xb ee ff [D,IDX] E0 xb [IDX2] E0 xb ee ff MOTOROLA INSTRUCTION REFERENCE CPU12 A-16 REFERENCE MANUAL...
  • Page 355 Transfer Register to Register r1 and r2 may be A, B, CCR, D, X, Y, or SP (CCR) ⇒ A B7 20 – – – – – – – – Translates to TFR CCR , A CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-17...
  • Page 356 X points at first element in S list. Y points at first element in F list. All S and F elements are 8-bits. If interrupted, six extra bytes of stack used for intermediate values MOTOROLA INSTRUCTION REFERENCE CPU12 A-18 REFERENCE MANUAL...
  • Page 357 IM — Immediate RL — Relative SP — Special Cycle counts are for single-chip mode with 16-bit internal buses. Stack location (internal or external), external bus width, and operand alignment can affect actual execution time. CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-19...
  • Page 362 10 = D (16-bit) 11 = see accumulator D offset indexed-indirect rr can specify X, Y, SP, or PC 111rr111 [D,r] Accumulator D offset indexed-indirect rr can specify X, Y, SP, or PC MOTOROLA INSTRUCTION REFERENCE CPU12 A-24 REFERENCE MANUAL...
  • Page 363 IBEQ IBEQ IBNE IBNE (–) (–) (–) (–) (–) (–) postbyte (hex) counter used _BEQ (–) sign of 9-bit relative branch offset branch condition (lower eight bits are an extension byte following postbyte) CPU12 INSTRUCTION REFERENCE MOTOROLA REFERENCE MANUAL A-25...
  • Page 364 MOTOROLA INSTRUCTION REFERENCE CPU12 A-26 REFERENCE MANUAL...
  • Page 365: B.1 Cpu12 Design Goals

    CPU12 instructions. This translation is performed by the assembler so there is no need to modify an old M68HC11 program in order to assemble it for the CPU12. In fact, the M68HC11 mnemonics can be used in new CPU12 programs. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL...
  • Page 366 Kbyte M68HC11 assembly code program, was reassembled for the CPU12. The re- sulting object code is six bytes smaller than the M68HC11 code. It is fair to conclude that M68HC11 code can be reassembled with very little change in size. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
  • Page 367: B.3 Programmer's Model And Stacking

    1974. The M6800 was strictly an 8-bit machine, with 8-bit data buses and 8-bit instructions. As Motorola devices evolved from the M6800 to the M68HC11, a number of 16-bit instructions were added, but the data buses remained eight bits wide, so these instructions were performed as sequences of 8-bit opera- tions.
  • Page 368 If the queue is aligned at the start of an instruction with an odd byte count, the last byte of object code shares a queue word with the opcode of the next instruction. Since this word holds part of the next instruction, the queue cannot ad- MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
  • Page 369 $01F2. With the last-used CPU12 stack, if the SP = $01F0 when execution begins, the sequence is: load X from $01F0:01F1; SP = SP + 2; and the SP again ends up at $01F2. The second sequence requires one less stack pointer adjustment. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL...
  • Page 370: B.5 Improved Indexing

    5-, 9-, or 16-bit signed off- sets. This approach eliminates the differences between X and Y register use and dra- matically enhances indexed addressing capabilities. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
  • Page 371 (–32,768 to +32767) or unsigned (0 to 65,535) value. In 16- bit constant offset mode, the offset is supplied in two extension bytes after the opcode and postbyte. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL...
  • Page 372 This reduces the loop execution time from 15 cycles to six cycles. This re- duction, combined with the 8-MHz bus speed of the M68HC12 family, can have signif- icant effects. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12 REFERENCE MANUAL...
  • Page 373: B.6 Improved Performance

    B.6.2 Fast Math The CPU12 has some of the fastest math ever designed into a Motorola general-pur- pose MCU. Much of the speed is due to a 20-bit ALU that can perform two smaller op- erations simultaneously.
  • Page 374 CPU12 assembly language programs written from scratch tend to be 30% smaller than equivalent programs written for the M68HC11. This figure has been indepen- dently qualified by Motorola programmers and an independent C compiler vendor. The major contributors to the reduction appear to be improved indexed addressing and the universal transfer/exchange instruction.
  • Page 375: B.7 Additional Functions

    Increment and Branch if Equal to Zero (Looping Primitive) IBNE Relative Increment and Branch if Not Equal to Zero (Looping Primitive) Signed Integer Divide D/X ⇒ X(Q) and D(R) (Signed) IDIVS Inherent CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL B-11...
  • Page 376 Table Lookup and Interpolate (8-bit Entries) TBNE Relative Test Register and Branch if Not Equal to Zero (Looping Primitive) Inherent Transfer Register Contents to Another Register Special Weighted Average (Fuzzy Logic Support) MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12 B-12 REFERENCE MANUAL...
  • Page 377 B.7.4 Long Branches All of the branch instructions from the M68HC11 are also available with 16-bit offsets which allows them to reach any location in the 64-Kbyte address space. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL B-13...
  • Page 378 A kernel written for the M68HC11 required about 250 bytes and executed in about 750 milliseconds. The CPU12 kernel uses about 50 bytes and executes in about 50 microseconds. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
  • Page 379 LDX 5,SP+ loads X with the value on the bottom of the stack and deallocates five bytes from the stack in a single operation that takes only two bytes of object code. CPU12 M68HC11 TO M68HC12 UPGRADE PATH MOTOROLA REFERENCE MANUAL B-15...
  • Page 380 CALL instruction, the destination page value is provided as immedi- ate data in the instruction object code. CALL and RTC execute correctly in the normal 64-Kbyte address space, thus providing for portable code. MOTOROLA M68HC11 TO M68HC12 UPGRADE PATH CPU12...
  • Page 381: C.1 Data Types

    HLL. Larger program ROM size require- ments translate into increased system costs. Motorola solicited the cooperation of third-party software developers to assure that the CPU12 instruction set would meet the needs of a more efficient generation of compil- ers.
  • Page 382 Next, the called subroutine establishes a new frame pointer by executing a TFR S,X. Space is allocated for local variables by executing an LEAS –n,S, where n is the num- ber of bytes needed for local variables. MOTOROLA HIGH-LEVEL LANGUAGE SUPPORT CPU12...
  • Page 383: C.3 Increment And Decrement Operators

    16-bit value (the size of an integer data type). The 16-bit C value would need to be sign-extended into the upper 16-bits of the 32-bit EDIVS numerator before the divide operation. CPU12 HIGH-LEVEL LANGUAGE SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 384: C.5 Conditional If Constructs

    Since the CALL instruction is uninterruptible, this eliminates the need to sep- arately mask off interrupts during the context switch. MOTOROLA HIGH-LEVEL LANGUAGE SUPPORT CPU12...
  • Page 385: C.9 Instruction Set Orthogonality

    Greater regularity of the instruction makes it possible to implement compilers more efficiently, because operation is more consistent, and fewer special cases must be handled. CPU12 HIGH-LEVEL LANGUAGE SUPPORT MOTOROLA REFERENCE MANUAL...
  • Page 386 MOTOROLA HIGH-LEVEL LANGUAGE SUPPORT CPU12 REFERENCE MANUAL...
  • Page 387 16,y d113 a9 80 adca d18b a9 b7 adca 8,sp+ d115 a9 00 adca d18d a9 37 adca 8,x+ d117 a9 40 adca d18f a9 77 adca 8,y+ d119 a9 af adca 1,-sp CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL...
  • Page 388 77 00 55 d2d0 0e a0 55 fc brset 1,+sp #$55 * d228 77 01 88 d2d4 0e a0 55 fc brset 1,+sp,$55,* d22b 47 asra d2d8 0e a0 55 fc brset 1,+sp,#$55,* MOTOROLA ASSEMBLY LISTING CPU12 REFERENCE MANUAL...
  • Page 389 8,+y d39a 4b 01 55 call 1,x $55 d459 e1 c0 cmpb d39d 4b 41 55 call 1,y $55 d45b e1 80 cmpb d3a0 4b bf 55 call 1,sp- $55 d45d e1 00 cmpb CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL...
  • Page 390 61 b8 8,sp- d4eb e1 e2 01 88 cmpb ext,x d581 61 38 8,x- d4ef e1 ea 01 88 cmpb ext,y d583 61 78 8,y- d4f3 e1 f8 37 cmpb ind,pc d585 61 f4 a,sp MOTOROLA ASSEMBLY LISTING CPU12 REFERENCE MANUAL...
  • Page 391 5f -1,y d613 ac 81 1,sp d6ab af 90 -16,sp d615 ac 01 d6ad af 10 -16,x d617 ac 41 d6af af 50 -16,y d619 ac bf 1,sp- d6b1 af f1 ef -17,sp CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL...
  • Page 392 1,+sp d7d3 ae ee d747 ae 20 1,+x d7d5 9e 55 d749 ae 60 1,+y d7d7 9e 55 d74b ae a7 8,+sp d7d9 be 01 88 d74d ae 27 8,+x d7dc be 01 88 MOTOROLA ASSEMBLY LISTING CPU12 REFERENCE MANUAL...
  • Page 393 10 16,sp d908 63 52 -small,y d871 ad e0 10 16,x d90a 63 c0 0,pc d874 ad e8 10 16,y d90c 63 80 0,sp d877 ad b7 8,sp+ d90e 63 00 CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL...
  • Page 394 8,+x da7d 18 1a f8 37 emaxd ind,pc d9aa 18 1a 67 emaxd 8,+y da81 18 1a f0 37 emaxd ind,sp d9ad 18 1a c0 emaxd da85 18 1a e0 37 emaxd ind,x MOTOROLA ASSEMBLY LISTING CPU12 REFERENCE MANUAL...
  • Page 395 18 1e f4 emaxm a,sp dc28 18 1b 8f emind 15,sp db54 18 1e e4 emaxm dc2b 18 1b 0f emind 15,x db57 18 1e ec emaxm dc2e 18 1b 4f emind 15,y CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL...
  • Page 396 18 1f 30 eminm 1,x+ ddbf a8 10 eora -16,x dd01 18 1f 70 eminm 1,y+ ddc1 a8 50 eora -16,y dd04 18 1f 81 eminm 1,sp ddc3 a8 f1 ef eora -17,sp MOTOROLA ASSEMBLY LISTING CPU12 D-10 REFERENCE MANUAL...
  • Page 397 55 eorb de59 e8 60 eorb 1,+y dee7 d8 55 eorb de5b e8 a7 eorb 8,+sp dee9 f8 01 88 eorb de5d e8 27 eorb 8,+x deec f8 01 88 eorb CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-11...
  • Page 398 62 ec df76 b7 e7 y sp e004 62 f5 b,sp df78 b7 e5 e006 62 e5 df7a b7 e6 e008 62 ed df7c 18 11 fdiv e00a 62 f6 d,sp MOTOROLA ASSEMBLY LISTING CPU12 D-12 REFERENCE MANUAL...
  • Page 399 05 7f 1,y- e12f 15 92 -small,sp e096 05 f8 7d 125,pc e131 15 12 -small,x e099 05 f0 7d 125,sp e133 15 52 -small,y e09c 05 e0 7d 125,x e135 15 c0 0,pc CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-13...
  • Page 400 18 2b ff fc lbmi e27b a6 38 ldaa 8,x- e1e1 18 26 ff fc lbne e27d a6 78 ldaa 8,y- e1e5 18 2a ff fc lbpl e27f a6 f4 ldaa a,sp MOTOROLA ASSEMBLY LISTING CPU12 D-14 REFERENCE MANUAL...
  • Page 401 01 ldab e3a5 ec 90 -16,sp e30e e6 41 ldab e3a7 ec 10 -16,x e310 e6 bf ldab 1,sp- e3a9 ec 50 -16,y e312 e6 3f ldab 1,x- e3ab ec f1 ef -17,sp CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-15...
  • Page 402 20 1,+x e4cf df 55 e443 ef 60 1,+y e4d1 ff 01 88 e445 ef a7 8,+sp e4d4 ef f2 01 88 ext,sp e447 ef 27 8,+x e4d8 ef e2 01 88 ext,x MOTOROLA ASSEMBLY LISTING CPU12 D-16 REFERENCE MANUAL...
  • Page 403 10 16,y e5ff ed b0 1,sp+ e56c ee b7 8,sp+ e601 ed 30 1,x+ e56e ee 37 8,x+ e603 ed 70 1,y+ e570 ee 77 8,y+ e605 ed 81 1,sp CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-17...
  • Page 404 -1,x e72e 1a 67 leax 8,+y e698 1b 5f leas -1,y e730 1a c0 leax e69a 1b 90 leas -16,sp e732 1a 80 leax e69c 1b 10 leas -16,x e734 1a 00 leax MOTOROLA ASSEMBLY LISTING CPU12 D-18 REFERENCE MANUAL...
  • Page 405 19 e4 leay e7c6 1a e0 37 leax ind,x e856 19 ec leay e7c9 1a e8 37 leax ind,y e858 19 f5 leay b,sp e7cc 1a ce leax small,pc e85a 19 e5 leay CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-19...
  • Page 406 -small,y e8e9 68 0f 15,x e97d 64 c0 0,pc e8eb 68 4f 15,y e97f 64 80 0,sp e8ed 68 f0 10 16,sp e981 64 00 e8f0 68 e0 10 16,x e983 64 40 MOTOROLA ASSEMBLY LISTING CPU12 D-20 REFERENCE MANUAL...
  • Page 407 18 18 2f maxa 1,-x eaf8 18 18 4e maxa small,y ea21 18 18 6f maxa 1,-y eafb 18 1c a0 maxm 1,+sp ea24 18 18 a8 maxa 8,-sp eafe 18 1c 20 maxm 1,+x CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-21...
  • Page 408 18 1c e6 maxm eca0 18 19 b7 mina 8,sp+ ebcb 18 1c ee maxm eca3 18 19 37 mina 8,x+ ebce 18 1c f2 01 88 maxm ext,sp eca6 18 19 77 mina 8,y+ MOTOROLA ASSEMBLY LISTING CPU12 D-22 REFERENCE MANUAL...
  • Page 409 18 0a 6b 80 movb 5,-y 0,sp ed76 18 1d 7f minm 1,y- ee4d 18 0a 6b 80 movb 5,-y,0,sp ed79 18 1d f8 7d minm 125,pc ee51 18 08 22 72 movb #immed 3,+x CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-23...
  • Page 410 -1,sp 3,+x ef59 18 0a 22 e4 movb 3,+x a,x f06f 18 0a 9f 6b movb -1,sp 5,-y ef5d 18 0a 22 ec movb 3,+x a,y f073 18 0a 9f 85 movb -1,sp 5,sp MOTOROLA ASSEMBLY LISTING CPU12 D-24 REFERENCE MANUAL...
  • Page 411 18 0d 70 01 88 movb 1,y+ ext f296 18 0a 6b 4f movb 5,-y 15,y f18c 18 0a 81 22 movb 1,sp 3,+x f29a 18 0a 6b b7 movb 5,-y 8,sp+ CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-25...
  • Page 412 18 0a 85 81 movb 5,sp 1,sp f4b5 18 0a e5 22 movb b,x 3,+x f3a6 18 0a 85 01 movb 5,sp 1,x f4b9 18 0a e5 6b movb b,x 5,-y MOTOROLA ASSEMBLY LISTING CPU12 D-26 REFERENCE MANUAL...
  • Page 413 18 09 e4 01 88 movb ext a,x f717 18 02 22 28 movw 3,+x 8,-x f5f5 18 09 ec 01 88 movb ext a,y f71b 18 02 22 68 movw 3,+x 8,-y CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-27...
  • Page 414 18 02 00 6b movw ,x 5,-y f93d 18 05 12 01 88 movw -small,x ext f829 18 02 00 85 movw ,x 5,sp f942 18 02 52 22 movw -small,y 3,+x MOTOROLA ASSEMBLY LISTING CPU12 D-28 REFERENCE MANUAL...
  • Page 415 5,sp 1,+sp fa54 18 02 6b 40 movw 5,-y ,y fb60 18 02 85 20 movw 5,sp 1,+x fa58 18 02 6b af movw 5,-y 1,-sp fb64 18 02 85 60 movw 5,sp 1,+y CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-29...
  • Page 416 18 02 77 22 movw 8,y+ 3,+x fd8e 18 01 28 01 88 movw ext 8,-x fc6f 18 02 77 6b movw 8,y+ 5,-y fd93 18 01 68 01 88 movw ext 8,-y MOTOROLA ASSEMBLY LISTING CPU12 D-30 REFERENCE MANUAL...
  • Page 417 1,+y ff48 70 01 88 febb 60 a7 8,+sp ff4b 70 01 88 febd 60 27 8,+x ff4e 60 f2 01 88 ext,sp febf 60 67 8,+y ff52 60 e2 01 88 ext,x CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-31...
  • Page 418 0,sp ffde aa f0 10 oraa 16,sp 0074 ea 00 orab ffe1 aa e0 10 oraa 16,x 0076 ea 40 orab ffe4 aa e8 10 oraa 16,y 0078 ea b0 orab 1,sp+ MOTOROLA ASSEMBLY LISTING CPU12 D-32 REFERENCE MANUAL...
  • Page 419 00fe 65 20 1,+x 018c 75 00 55 0100 65 60 1,+y 018f 75 01 88 0102 65 a7 8,+sp 0192 75 01 88 0104 65 27 8,+x 0195 65 f2 01 88 ext,sp CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-33...
  • Page 420 16,x 02b5 a2 52 sbca -small,y 0226 66 e8 10 16,y 02b7 a2 c0 sbca 0,pc 0229 66 b7 8,sp+ 02b9 a2 80 sbca 0,sp 022b 66 37 8,x+ 02bb a2 00 sbca MOTOROLA ASSEMBLY LISTING CPU12 D-34 REFERENCE MANUAL...
  • Page 421 034e e2 2f sbcb 1,-x 03e7 e2 e8 37 sbcb ind,y 0350 e2 6f sbcb 1,-y 03ea e2 ce sbcb small,pc 0352 e2 a8 sbcb 8,-sp 03ec e2 8e sbcb small,sp CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-35...
  • Page 422 -17,x 046f 6a 3f staa 1,x- 0508 6b e9 ef stab -17,y 0471 6a 7f staa 1,y- 050b 6b d2 stab -small,pc 0473 6a f8 7d staa 125,pc 050d 6b 92 stab -small,sp MOTOROLA ASSEMBLY LISTING CPU12 D-36 REFERENCE MANUAL...
  • Page 423 059e 6c 80 0632 6c ea 01 88 ext,y 05a0 6c 00 0636 6c f8 37 ind,pc 05a2 6c 40 0639 6c f0 37 ind,sp 05a4 6c af 1,-sp 063c 6c e0 37 ind,x CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-37...
  • Page 424 06c6 6f 38 8,x- 0758 6e f8 7d 125,pc 06c8 6f 78 8,y- 075b 6e f0 7d 125,sp 06ca 6f f4 a,sp 075e 6e e0 7d 125,x 06cc 6f e4 0761 6e e8 7d 125,y MOTOROLA ASSEMBLY LISTING CPU12 D-38 REFERENCE MANUAL...
  • Page 425 07f2 6d 92 -small,sp 0889 a0 40 suba 07f4 6d 12 -small,x 088b a0 af suba 1,-sp 07f6 6d 52 -small,y 088d a0 2f suba 1,-x 07f8 6d c0 0,pc 088f a0 6f suba 1,-y CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-39...
  • Page 426 09b0 e0 e4 subb 0924 a0 ce suba small,pc 09b2 e0 ec subb 0926 a0 8e suba small,sp 09b4 e0 f5 subb b,sp 0928 a0 0e suba small,x 09b6 e0 e5 subb MOTOROLA ASSEMBLY LISTING CPU12 D-40 REFERENCE MANUAL...
  • Page 427 0a47 a3 f8 7d subd 125,pc 0ade b7 22 ccr ccr 0a4a a3 f0 7d subd 125,sp 0ae0 b7 24 ccr d 0a4d a3 e0 7d subd 125,x 0ae2 b7 27 ccr sp CPU12 ASSEMBLY LISTING MOTOROLA REFERENCE MANUAL D-41...
  • Page 428 0b5b e7 12 -small,x 0bef 0a 0b5d e7 52 -small,y 0b5f e7 c0 0,pc 0b61 e7 80 0,sp 0b63 e7 00 0b65 e7 40 0b67 e7 b0 1,sp+ 0b69 e7 30 1,x+ MOTOROLA ASSEMBLY LISTING CPU12 D-42 REFERENCE MANUAL...
  • Page 429 ASLA instruction 6-20 Branch instructions 3-4, 4-4 to 4-5, 5-13, C-4 ASLB instruction 6-21 Bit-condition 4-4 to 4-5, 5-16, 6-45, 6-47 ASLD instruction 6-22 Long 4-4 to 4-5, 5-13, 6-104 to 6-121, B-13 ASR instruction 6-23 CPU12 MOTOROLA REFERENCE MANUAL...
  • Page 430 Clock monitor reset 7-3 CPS instruction 6-66 CLR instruction 6-56 CPU wait 6-213 CLRA instruction 6-57 CPX instruction 6-67 CLRB instruction 6-58 CPY instruction 6-68 CLV instruction 6-59 Cycle code letters 6-5 CMPA instruction 6-60 Cycle counts B-9 MOTOROLA CPU12 REFERENCE MANUAL...
  • Page 431 Custom programming 9-26 Vectors 7-1, 7-6 Defuzzification 5-9, 9-6, 9-22 to 9-24, 9-26, 9-29 Exchange instructions 5-2, 6-90, 6-215 to 6-216, Fuzzification 5-9, 9-3, 9-26 B-11, B-13 Inference kernel 5-9, 9-2, 9-7 Postbyte encoding A-24 Inputs 5-9, 9-30 CPU12 MOTOROLA REFERENCE MANUAL...
  • Page 432 X mask bit 2-3, 6-189, 6-213, 7-4 6-100, 6-126, 6-128 to 6-130, 6-158, 6-164, INX instruction 6-100 6-166, 6-168, 6-177, 6-185, 6-191, 6-196, INY instruction 6-101 6-200 to 6-203, 6-209, 6-211, 6-215 Y 3-5, 6-10, 6-68, 6-70 to 6-71, 6-77 to 6-80, MOTOROLA CPU12 REFERENCE MANUAL...
  • Page 433 6-214 Postbyte encoding A-25 M68HC11 compatibility 3-2, B-1 Low-power stop 5-21, 6-189 M68HC11 instruction mnemonics B-1 LSL instruction 6-131 LSL mnemonics 5-8 LSLA instruction 6-132 N status bit 2-4, 6-41, 6-43, 6-115, 6-117 LSLB instruction 6-133 CPU12 MOTOROLA REFERENCE MANUAL...
  • Page 434 6-103, 6-128 to 6-130, 6-144 to 6-145, 6-150, SBA instruction 6-179 6-177 to 6-178, 6-196, 6-201, 6-205 SBCA instruction 6-180 Program word access cycle 6-6 SBCB instruction 6-181 Programming model 1-1, 2-1, B-3 SEC instruction 6-182 MOTOROLA CPU12 REFERENCE MANUAL...
  • Page 435 Branch 5-13 STY instruction 6-192 Clear, complement, and negate 5-6 SUBA instruction 6-193 Compare and test 5-5 SUBB instruction 6-194 Condition code 5-21 SUBD instruction 6-195 Decrement and increment 5-4 Subroutine instructions 5-17 Fuzzy logic 5-9 CPU12 MOTOROLA REFERENCE MANUAL...
  • Page 436 9-17 to 9-20, 9-22, 9-29 Word moves 6-145 Write PPAGE cycle 6-5 Write 16-bit data cycle 6-6 Write 8-bit data cycle 6-6 X mask bit 2-3, 6-90, 6-162, 6-177, 6-189, 6-198, 6-203, 6-213 XGDX instruction 6-215 XGDY instruction 6-216 MOTOROLA CPU12 REFERENCE MANUAL...
  • Page 437 Table B-3, last row (EMACS) math operation corrected and two occurrences of B-10 “per iteration” removed. B-13 Section B.7.2, first sentence, “six transfer instructions” is now “eight transfer instructions.” Minor grammatical and typographic corrections to improve consistency and presentation. General New index markers. CPU12 SUMMARY OF CHANGES MOTOROLA REFERENCE MANUAL...
  • Page 438 MOTOROLA SUMMARY OF CHANGES CPU12 REFERENCE MANUAL...
  • Page 440 Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.

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