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V DD
CTL
D P0
PC out
D P1
D P2
D P3
PULSE
PC in
GENERATOR 1
F
Q1/C2
G
PULSE
C1
GENERATOR 2
PE
V SS
CTL
D P0
D P1
D P2
D P3
PC in
F
G
PULSE
C1
GENERATOR
PE
D P0
D P1
D P2
D P3
PULSE
Q1/C2
GENERATOR
PC in
F
G
C1
CTL
PE
20 ns
90%
Q1/C2
50%
10%
t PLH
90%
50%
"0"
10%
t TLH
MC14568B
6–464
SWITCHING TIME TEST CIRCUITS AND WAVEFORMS
A LAGS B, PC out IS LOW.
V DD
2
"0" out REF
10 k
B
LD
PC in
C L
C L
PG1
A
LD
"0"
PC out
Figure 1. Phase Comparator
V DD
PC out
LD
Q1/C2
C L
"0"
V SS
Figure 2. Counter D1
V DD
PC out
LD
"0"
V SS
C L
t W(Q1/C2)
20 ns
t PHL
f in f max
t THL
a.
Figure 3. Counter D2
A LEADS B, PC out IS HIGH.
50%
50%
t PLH
t THL
90%
t PHL
t TLH
THREE–STATE
THREE–STATE
t PHL
20 ns
90%
C1
50%
10%
90%
Q1/C2
50%
10%
t TLH
PULSE
GENERATOR 1
PULSE
GENERATOR 2
50%
Q1/C2 = PG 1
20 ns
90%
PE = PG2
50%
10%
t W(PE)
"0"
* N is the value programmed on the D P Inputs.
MOTOROLA CMOS LOGIC DATA
20 ns
20 ns
t W(PC in )
90%
10%
t PLH
t PLH
10%
t PHL
75%
25%
t PLH
20 ns
t W(C1)
f in f max
t PHL
t THL
V DD
D P0
D P1
PC out
D P2
LD
D P3
Q1/C2
PC in
F
G
"0"
C1
C L
CTL
PE
V SS
N PULSES*
20 ns
b.
V OH
V OL
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