Motorola CMOS Logic Manual page 475

7
C in
15
A1
14
B1
1
A2
2
B2
3
A3
4
B3
5
A4
6
B4
V DD = PIN 16
V SS = PIN 8
One MC14560B and MC14561B permit a
BCD digit to be added to or subtracted from
a second digit, such as in this typical config-
uration. A second MC14561B permits either
digit to be added to or subtracted from the
other, or either word to appear unmodified at
the output.
TRUTH TABLE
Zero Add/Subtract Result
0 0 B plus A
0 1 B minus A
1 X
X = Don't Care
MOTOROLA CMOS LOGIC DATA
FUNCTIONAL EQUIVALENT LOGIC DIAGRAM
ADD/SUBTRACT
ZERO
B
Figure 3. Parallel Add/Subtract Circuit
MC14561B
A1 F1
A2
A1
A3 F2
A4
COMP F3
COMP
Z F4
B1
MC14561B
A1 F1
A2
A10
A3 F2
A4
COMP F3
COMP
Z F4
B10
13
S1
12
S2
11
S3
10
S4
9
C out
MC14560B
C in S1
A1
A2 S2
A3 UNITS
A4 S3
B1
B2 S4
B3
B4 C out
MC14560B
C in S1
A1
A2 S2
A3
TENS
A4 S3
B1
B2 S4
B3
B4 C out
MC14560B
6–437