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Motorola CMOS Logic Manual page 354

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Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
ELECTRICAL CHARACTERISTICS
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
Characteristic
Output Voltage
"0" Level
V in = V DD or 0
"1" Level
V in = 0 or V DD
Input Voltage
"0" Level
(V O = 4.5 or 0.5 Vdc)
(V O = 9.0 or 1.0 Vdc)
(V O = 13.5 or 1.5 Vdc)
"1" Level
(V O = 0.5 or 4.5 Vdc)
(V O = 1.0 or 9.0 Vdc)
(V O = 1.5 or 13.5 Vdc)
Output Drive Current
(V OH = 2.5 Vdc)
(V OH = 4.6 Vdc)
(V OH = 9.5 Vdc)
(V OH = 13.5 Vdc)
(V OL = 0.4 Vdc)
(V OL = 0.5 Vdc)
(V OL = 1.5 Vdc)
Input Current
Input Capacitance
(V in = 0)
Quiescent Current
(Per Package)
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(C L = 50 pF on all outputs, all
buffers switching)
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
** The formulas given are for the typical characteristics only at 25 _ C.
†To calculate total supply current at loads other than 50 pF:
I T (C L ) = I T (50 pF) + (C L – 50) Vfk
where: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.0012.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V in and
V out should be constrained to the range V SS
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V SS or V DD ). Unused outputs must be left open.
MC14527B
6–316
(Voltages Referenced to V SS )
V DD
Vdc
Symbol
Min
V OL
5.0
10
15
V OH
5.0
4.95
10
9.95
15
14.95
V IL
5.0
10
15
V IH
5.0
10
15
I OH
Source
5.0
– 3.0
5.0
– 0.64
10
– 1.6
15
– 4.2
Sink
I OL
5.0
0.64
10
15
I in
15
C in
I DD
5.0
10
15
I T
5.0
10
15
(V in or V out )
– 55 _ C
25 _ C
Max
Min
Typ #
0.05
0
0.05
0
0.05
0
4.95
5.0
9.95
10
14.95
15
1.5
2.25
3.0
4.50
4.0
6.75
3.5
3.5
2.75
7.0
7.0
5.50
11
11
8.25
– 2.4
– 4.2
– 0.51
– 0.88
– 1.3
– 2.25
– 3.4
– 8.8
0.51
0.88
1.6
1.3
2.25
4.2
3.4
8.8
0.1
0.00001
5.0
5.0
0.005
10
0.010
20
0.015
I T = (0.85 µA/kHz) f + I DD
I T = (1.75 µA/kHz) f + I DD
I T = (2.60 µA/kHz) f + I DD
V DD .
125 _ C
Max
Min
Max
0.05
0.05
0.05
0.05
0.05
0.05
4.95
9.95
14.95
1.5
1.5
3.0
3.0
4.0
4.0
3.5
7.0
11
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
0.1
1.0
7.5
5.0
150
10
300
20
600
PIN ASSIGNMENT
"9"
1
16
V DD
C
2
15
B
D
3
14
A
S
4
13
CLEAR
OUT
5
12
CASC
OUT
6
11
E in
E out
7
10
ST
V SS
8
9
CLOCK
MOTOROLA CMOS LOGIC DATA
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
µAdc
pF
µAdc
µAdc

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