Motorola CMOS Logic Manual page 553

RESET 2
DATA 3
STROBE 6
ENABLE 4
A0 7
A1 8
A2 10
(M.S.B)
D7
1
t PLH
RESET
A0, A1, A2
DATA
STROBE
ENABLE
* 1.4 V with V DD = 5.0 V
NOTES:
1. High–impedance output state (another device controls bus).
2. Output Load as for MC14597B.
MOTOROLA CMOS LOGIC DATA
MC14598B FUNCTION DIAGRAM
TO OTHER
LATCHES
TO OTHER
LATCHES ZERO
SELECT
ADDRESS
DECODER
MC14598B TIMING DIAGRAM
90%
50%
10%
t THL
50%
t PHL
t W
90%
10%
20 ns
*
EACH LATCH
ADDITIONAL 7 LATCHES
t PLH
t TLH
50%
t su t h
90%
50%
10%
20 ns t W
t W
V DD
1 D0
V SS
17 D1
16 D2
15 D3
14 D4
13 D5
12 D6
11 D7
90%
10%
20 ns
90%
10%
t su t h
MC14597B MC14598B
6–515