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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-to-64 Bit Variable Length
Shift Register
The MC14557B is a static clocked serial shift register whose length may
be programmed to be any number of bits between 1 and 64. The number of
bits selected is equal to the sum of the subscripts of the enabled Length
Control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be
selected from the A or B data inputs with the A/B select input. This feature is
useful for recirculation purposes. A Clock Enable (CE) input is provided to
allow gating of the clock or negative edge clocking capability.
The device can be effectively used for variable digital delay lines or simply
to implement odd length shift registers.
1–64 Bit Programmable Length
Q and Q Serial Buffered Outputs
Asynchronous Master Reset
All Inputs Buffered
No Limit On Clock Rise and Fall Times
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
MAXIMUM RATINGS*
(Voltages Referenced to V SS )
Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
Symbol
Parameter
V DD
DC Supply Voltage
V in , V out
Input or Output Voltage (DC or Transient)
I in , I out
Input or Output Current (DC or Transient),
per Pin
P D
Power Dissipation, per Package†
T stg
Storage Temperature
T L
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic "P and D/DW" Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic "L" Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
LENGTH SELECT TRUTH TABLE
L32
L16
L8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NOTE: Length equals the sum of the binary length control
subscripts plus one.
MOTOROLA CMOS LOGIC DATA
Value
– 0.5 to + 18.0
– 0.5 to V DD + 0.5
500
– 65 to + 150
260
L4
L2
L1
Register Length
0
0
0
1 Bit
0
0
0
0
1
1
2 Bits
2 Bit
0
0
1
1
0
0
3 Bits
3 Bits
0
0
1
1
1
1
4 Bits
4 Bits
1
1
0
0
0
0
5 Bits
5 Bits
1
1
0
0
1
1
6 Bits
6 Bits
0
0
0
0
0
0
33 Bits
33 Bit
0
0
0
0
1
1
34 Bits
34 Bits
1
0
0
61 Bits
1
1
1
62 Bits
1
1
0
63 Bits
1
1
0
0
1
1
64 Bits
64 Bit
T A = – 55 to 125 C for all packages.
Unit
V
V
10
mA
mW
_ C
_ C
15
14
13
12
Rst
0
0
0
0
1
Q is the output of the first selected shift
register stage.
X = Don't Care
MC14557B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBDW
SOIC
BLOCK DIAGRAM
3
RESET
4
CLOCK
5
CE
6
B
Q
10
7
A
9
A/B SELECT
2
L1
1
L2
L4
Q
11
L8
L16
L32
V DD = PIN 16
V SS = PIN 8
TRUTH TABLE
Inputs
Output
A/B
Clock
CE
Q
0
0
B
1
0
A
0
1
B
1
1
A
X
X
X
0
MC14557B
6–425
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