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500 pF
PE
CARRY IN
R
UP/DOWN
PULSE
CLOCK
GENERATOR
P0
P1
P2
P3
RESET
9
PRESET
1
ENABLE
CLOCK
15
CARRY OUT
7
CARRY IN
5
UP/DOWN
10
TOGGLE FLIP–FLOP
PARALLEL IN
MOTOROLA CMOS LOGIC DATA
V DD
I D
0.01 µF
CERAMIC
Q0
Q1
Q2
Q3
C L
CARRY
C L
OUT
C L
Figure 1. Power Dissipation Test Circuit and Waveform
LOGIC DIAGRAM
P0
Q0
4
6
P
PE
Q
C
T
Q
P
PE
Q
C
T
Q
20 ns
C L
CLOCK
C L
P1
Q1
P2
12
11
13
P
P
PE
Q
PE
Q
C
C
T
Q
T
Q
FLIP–FLOP FUNCTIONAL TRUTH TABLE
Preset
Enable
Clock
1
X
0
0
0
X = Don't Care
20 ns
V DD
90%
50%
10%
V SS
VARIABLE
WIDTH
Q2
P3
Q3
14
3
2
P
PE
Q
C
T
Q
T
Q n+1
X
Parallel In
0
Q n
1
Q n
X
Q n
MC14516B
6–283
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